Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbcL2KeA (ORCPT ); Thu, 29 Dec 2016 05:34:00 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:37953 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752380AbcL2Kd6 (ORCPT ); Thu, 29 Dec 2016 05:33:58 -0500 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 X-AuditID: b6c32a37-f79116d000000e56-5e-5864e6924412 Subject: Re: [PATCH 1/4] pinctrl: dt-bindings: samsung: add drive strength macros for Exynos5433 To: Andi Shyti , Tomasz Figa , Krzysztof Kozlowski , Sylwester Nawrocki , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Kukjin Kim , Javier Martinez Canillas Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Andi Shyti From: Chanwoo Choi Organization: Samsung Electronics Message-id: <6bf77b57-c2a4-2dff-9763-1cd1bfa23b9d@samsung.com> Date: Thu, 29 Dec 2016 19:33:53 +0900 User-Agent: Mozilla/5.0 (X11; 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So, I'd like you to use the EXYNOS5420_PIN_DRV_LVx instead of separate the definitions. I found the problem to handle the *_DRV register of Exynos5433. Because Exynos5433 has the different width length of *_DRV (PINCFG_TYPE_DRV) bitfields from Exynos542x as following. When I was sending the exynos5433 pinctrl patches, I was missing this issue. Exynos5422/Exynos5410 have two different bitfields in the same register to set the DRV_LVx as following: (n=0 to 7) [2n+1:2n] : 2bits 0x0 = 1x, 0x1 = 2x, 0x2 = 3x, 0x3 = 4x, [n+16:16] 0x0 = Fast Slew Rate, 0x1 = Slow Slew Rate, But, Exynos5433 has the following value for PIN_DRV_LVx without additional bitfields to separate 'Fast Slew Rate' and 'Slow Slew Rate'. Just exynos5433 defines the 'Fast Slew Rate(0x0 ~ 0x5)' and 'Slow Slew Rate (0x8 ~ 0xF)'. (n=0 to 7) [4n+3:4n] : 4 bits 0x0 = Fast Slew Rate 1x 0x1 = Fast Slew Rate 2x 0x2 = Fast Slew Rate 3x 0x3 = Fast Slew Rate 4x 0x4 = Fast Slew Rate 5x 0x5 = Fast Slew Rate 6x 0x8 = Slow Slew Rate 1x 0x9 = Slow Slew Rate 2x 0xA = Slow Slew Rate 3x 0xB = Slow Slew Rate 4x 0xC = Slow Slew Rate 5x 0xF = Slow Slew Rate 6x So, before this patch, we have to fix it to support the DRV reigster of Exynos5433. I'll fix it. > >> + >> #define EXYNOS_PIN_FUNC_INPUT 0 >> #define EXYNOS_PIN_FUNC_OUTPUT 1 >> #define EXYNOS_PIN_FUNC_2 2 >> > -- Regards, Chanwoo Choi