Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752370AbdCCXuP (ORCPT ); Fri, 3 Mar 2017 18:50:15 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:52406 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752151AbdCCXuM (ORCPT ); Fri, 3 Mar 2017 18:50:12 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D3EA16071E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 3 Mar 2017 15:50:09 -0800 From: Stephen Boyd To: Vlad Zakharov Cc: Michael Turquette , "linux-kernel@vger.kernel.org" , Jose Abreu , "devicetree@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" , "mark.rutland@arm.com" , "robh@kernel.org" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver Message-ID: <20170303235005.GV25384@codeaurora.org> References: <1487682670-4164-1-git-send-email-vzakhar@synopsys.com> <1488547113.2557.44.camel@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1488547113.2557.44.camel@synopsys.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1448 Lines: 37 On 03/03, Vlad Zakharov wrote: > Hi Michael, Stephen, > > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote: > > AXS10X boards manages it's clocks using various PLLs. These PLL has same > > dividers and corresponding control registers mapped to different addresses. > > So we add one common driver for such PLLs. > > > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and > > ODIV. Output clock value is managed using these dividers. > > > > We add pre-defined tables with supported rate values and appropriate > > configurations of IDIV, FBDIV and ODIV for each value. > > > > As of today we add support for PLLs that generate clock for the > > following devices: > > ?* ARC core on AXC CPU tiles. > > ?* ARC PGU on ARC SDP Mainboard. > > and more to come later. > > > > Acked-by: Rob Herring > > Signed-off-by: Vlad Zakharov > > Signed-off-by: Jose Abreu > > Cc: Michael Turquette > > Cc: Stephen Boyd > > Cc: Mark Rutland > > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it. > I haven't reviewed it yet. The merge window is upon us right now so I'll probably get to going through the queue this weekend/next week. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project