Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752224AbdCDATr (ORCPT ); Fri, 3 Mar 2017 19:19:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:32790 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751742AbdCDATp (ORCPT ); Fri, 3 Mar 2017 19:19:45 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E0CE860C7B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 3 Mar 2017 15:56:39 -0800 From: Stephen Boyd To: Maxime Ripard Cc: Chen-Yu Tsai , Michael Turquette , linux-clk , linux-arm-kernel , linux-kernel Subject: Re: [PATCH 4/5] clk: sunxi-ng: Add driver for A83T CCU Message-ID: <20170303235639.GW25384@codeaurora.org> References: <20170214033526.16977-1-wens@csie.org> <20170214033526.16977-5-wens@csie.org> <20170214095819.utsftcvti5zdmlmi@lukather> <20170215094954.h3wyaxlqkeb342yu@lukather> <20170301191705.GS25384@codeaurora.org> <20170303095333.hgxoli2h7clailvo@lukather> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170303095333.hgxoli2h7clailvo@lukather> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1918 Lines: 46 On 03/03, Maxime Ripard wrote: > On Wed, Mar 01, 2017 at 11:17:05AM -0800, Stephen Boyd wrote: > > > Can someone explain what the issue is? Could something like > > clk_get_phase() + clk_get_rate() tell us if we're in one mode > > vs. the other? > > So we have two modes of operation for that clock, old vs new (I know, > I didn't pick the names). > > The old mode is what we support right now. It has a combination of a > linear multiplier and divider, plus some phase controls. > > The new mode however disables the phase controls and adds post-divider > of 2 on the rate. > > We cannot really rely on the rate itself, since there's a huge overlap > between the rates we can obtain in the old and new modes. Same thing > for the phase, having a 0 deg phase is achieved both in the old and > new modes. > > To make things worse, the new mode is only available on one out of > three MMC controllers (and associated clocks), and that MMC controller > needs to set a bit as well to switch to the new mode if needed. So we > definitely needs some synchronisation there, and also to be able to > retrieve if the mode switching is available, and if we're already > using that mode. > > Mike agreed that the easiest way forward was to use a custom function. > Ok. Is there any need to change the mode dynamically at runtime? Or could it be decided once at clk driver probe time/boot time and detected via set_phase() failing when we're in the new mode? At least, it sounds like set_phase() should bail out there because it doesn't exist, although it could be argued that setting the phase to something it already is set to is valid and shouldn't return an error. I'm not saying I'm opposed to the custom function, just thinking of alternatives if MMC maintainers don't agree with the custom function. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project