Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752804AbdCHLKz (ORCPT ); Wed, 8 Mar 2017 06:10:55 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:34972 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770AbdCHLKt (ORCPT ); Wed, 8 Mar 2017 06:10:49 -0500 From: Magnus Damm To: joro@8bytes.org Cc: laurent.pinchart+renesas@ideasonboard.com, geert+renesas@glider.be, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, iommu@lists.linux-foundation.org, horms+renesas@verge.net.au, Magnus Damm , robin.murphy@arm.com, m.szyprowski@samsung.com Date: Wed, 08 Mar 2017 20:02:43 +0900 Message-Id: <148897096346.16106.12982552891354954137.sendpatchset@little-apple> In-Reply-To: <148897088333.16106.13237004440297956899.sendpatchset@little-apple> References: <148897088333.16106.13237004440297956899.sendpatchset@little-apple> Subject: [PATCH v3 08/09] iommu/ipmmu-vmsa: Allow two bit SL0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1993 Lines: 71 From: Magnus Damm Introduce support for two bit SL0 bitfield in IMTTBCR by using a separate feature flag. Signed-off-by: Magnus Damm --- Changes since V2: - None Changes since V1: - None drivers/iommu/ipmmu-vmsa.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) --- 0022/drivers/iommu/ipmmu-vmsa.c +++ work/drivers/iommu/ipmmu-vmsa.c 2017-03-08 18:33:07.630607110 +0900 @@ -38,6 +38,7 @@ struct ipmmu_features { bool has_cache_leaf_nodes; bool has_eight_ctx; bool setup_imbuscr; + bool twobit_imttbcr_sl0; }; struct ipmmu_vmsa_device { @@ -163,6 +164,10 @@ static void set_archdata(struct device * #define IMTTBCR_TSZ0_MASK (7 << 0) #define IMTTBCR_TSZ0_SHIFT O +#define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6) +#define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6) +#define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) + #define IMBUSCR 0x000c #define IMBUSCR_DVM (1 << 2) #define IMBUSCR_BUSSEL_SYS (0 << 0) @@ -406,6 +411,7 @@ static int ipmmu_domain_allocate_context static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) { u64 ttbr; + u32 tmp; int ret; /* @@ -458,9 +464,15 @@ static int ipmmu_domain_init_context(str * We use long descriptors with inner-shareable WBWA tables and allocate * the whole 32-bit VA space to TTBR0. */ + + if (domain->root->features->twobit_imttbcr_sl0) + tmp = IMTTBCR_SL0_TWOBIT_LVL_1; + else + tmp = IMTTBCR_SL0_LVL_1; + ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE | IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | - IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1); + IMTTBCR_IRGN0_WB_WA | tmp); /* MAIR0 */ ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]); @@ -1080,6 +1092,7 @@ static const struct ipmmu_features ipmmu .has_cache_leaf_nodes = false, .has_eight_ctx = false, .setup_imbuscr = true, + .twobit_imttbcr_sl0 = false, }; static const struct of_device_id ipmmu_of_ids[] = {