Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752655AbdCHPS1 convert rfc822-to-8bit (ORCPT ); Wed, 8 Mar 2017 10:18:27 -0500 Received: from mga09.intel.com ([134.134.136.24]:57973 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752466AbdCHPSY (ORCPT ); Wed, 8 Mar 2017 10:18:24 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,264,1486454400"; d="scan'208";a="942037302" From: "Liang, Kan" To: "peterz@infradead.org" , "mingo@kernel.org" , "linux-kernel@vger.kernel.org" CC: "eranian@google.com" , "ak@linux.intel.com" Subject: RE: [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont Thread-Topic: [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont Thread-Index: AQHSg6h6fCB+uk00Zk2+8TDDRpz08KGLNrpw Date: Wed, 8 Mar 2017 15:17:44 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536ADEB7@SHSMSX103.ccr.corp.intel.com> References: <1486711438-80058-1-git-send-email-kan.liang@intel.com> In-Reply-To: <1486711438-80058-1-git-send-email-kan.liang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWVkZmIwZDAtOWYzMy00MDk5LWI0MTQtMzM1ZTE5MDZhNTI4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ikh1NW5pSkkzeGRzdnFHbndFQVBWOStBWDZmcXZNUHlmSHFqRXBvcTZ2Y0U9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2124 Lines: 71 Ping. Any comments for this patch? Thanks, Kan > > From: Kan Liang > > Goldmont supports full Top Down level 1 metrics (FrontendBound, > Retiring, Backend Bound and Bad Speculation). > It has 3 wide pipeline. > > Signed-off-by: Kan Liang > --- > > Changes since V1: > - Change event list style > > arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index eb1484c..4244bed 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -1553,6 +1553,27 @@ static __initconst const u64 > slm_hw_cache_event_ids > }, > }; > > +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); > +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); > +/* UOPS_NOT_DELIVERED.ANY */ > +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, > "event=0x9c"); > +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ > +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, > "event=0xca,umask=0x02"); > +/* UOPS_RETIRED.ANY */ > +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, > "event=0xc2"); > +/* UOPS_ISSUED.ANY */ > +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, > "event=0x0e"); > + > +static struct attribute *glm_events_attrs[] = { > + EVENT_PTR(td_total_slots_glm), > + EVENT_PTR(td_total_slots_scale_glm), > + EVENT_PTR(td_fetch_bubbles_glm), > + EVENT_PTR(td_recovery_bubbles_glm), > + EVENT_PTR(td_slots_issued_glm), > + EVENT_PTR(td_slots_retired_glm), > + NULL > +}; > + > static struct extra_reg intel_glm_extra_regs[] __read_mostly = { > /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ > INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, > 0x760005ffbfull, RSP_0), > @@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void) > x86_pmu.pebs_prec_dist = true; > x86_pmu.lbr_pt_coexist = true; > x86_pmu.flags |= PMU_FL_HAS_RSP_1; > + x86_pmu.cpu_events = glm_events_attrs; > pr_cont("Goldmont events, "); > break; > > -- > 2.4.3