Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752945AbdCHPem (ORCPT ); Wed, 8 Mar 2017 10:34:42 -0500 Received: from smtprelay2.synopsys.com ([198.182.60.111]:34504 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750888AbdCHPed (ORCPT ); Wed, 8 Mar 2017 10:34:33 -0500 Subject: Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support To: Kishon Vijay Abraham I , Joao Pinto , Bjorn Helgaas , Jingoo Han References: <1487325042-28227-1-git-send-email-kishon@ti.com> <1487325042-28227-9-git-send-email-kishon@ti.com> <45e5288e-d11f-c855-af9b-692a42d878c6@synopsys.com> <58BE42B2.20305@ti.com> <02461be2-268d-485a-2bc4-3b148726d37d@synopsys.com> <58BFEC7D.3090608@ti.com> <35d539ba-956f-330e-c28d-b67c3d414578@synopsys.com> <58C00798.1030302@ti.com> CC: , , , , , , From: Joao Pinto Message-ID: <650c53fc-482c-feab-faa3-c30689d3d128@synopsys.com> Date: Wed, 8 Mar 2017 15:32:03 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <58C00798.1030302@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.107.19.101] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1632 Lines: 59 ?s 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu: > Hi, > > On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote: >> ?s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu: >>> Hi, >>> >>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote: >>>> >>>> Hi Kishon, >>>> >>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to >>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)? >>>>> >>>>> Yes of course, I will send you the definition soon. >>>> >>>> As promissed here is the definition for Inbound: >>>> >>>> +/* register address builder */ >>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \ >>>> + ((0x3 << 20) | (region << 9) | \ >>>> + (0x1 << 8) | (register << 2)) >>> >>> Cool, thanks! >> >> No problem! If you have doubts, please let me know. > > Okay, so this looks slightly different than the outbound macro since it takes > the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OFFSET > returns the offset which was used like > dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val); > > How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used? My original way was this one: +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \ + ((0x3 << 20) | (region << 9) | \ + (register << 2)) Bjorn then converted to offset: #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((0x3 << 20) | (region << 9)) and applied the <<2 shift to the ATU registers. So you can use: #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \ ((0x3 << 20) | (region << 9) | \ (0x1 << 8) Thanks. > > Thanks > Kishon >