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Subject: Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
To: Joao Pinto <Joao.Pinto@synopsys.com>,
        Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>
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From: Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <58C00798.1030302@ti.com>
Date: Wed, 8 Mar 2017 19:01:04 +0530
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Hi,

On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
> ?s 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>
>>> Hi Kishon,
>>>
>>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>>
>>>> Yes of course, I will send you the definition soon.
>>>
>>> As promissed here is the definition for Inbound:
>>>
>>> +/* register address builder */
>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)		\
>>> +					((0x3 << 20) | (region << 9) |	\
>>> +					(0x1 << 8) | (register << 2))
>>
>> Cool, thanks!
> 
> No problem! If you have doubts, please let me know.

Okay, so this looks slightly different than the outbound macro since it takes
the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
returns the offset which was used like
dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);

How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

Thanks
Kishon