Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932536AbdCIREk (ORCPT ); Thu, 9 Mar 2017 12:04:40 -0500 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:48756 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754691AbdCIREj (ORCPT ); Thu, 9 Mar 2017 12:04:39 -0500 From: Julia Cartwright To: Alban Bedel , Linus Walleij , Alexandre Courbot CC: , Thomas Gleixner , Subject: [PATCH 06/19] gpio: ath79: make use of raw_spinlock variants Date: Thu, 9 Mar 2017 10:21:53 -0600 Message-ID: <1774d7bad8bbc672372480f540dfc8f3d1592533.1489015238.git.julia@ni.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-03-09_13:,, signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-03-09_13:,, signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=30 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4338 Lines: 124 The ath79 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright --- drivers/gpio/gpio-ath79.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index dc37dbe4b46d..f33d4a5fe671 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -32,7 +32,7 @@ struct ath79_gpio_ctrl { struct gpio_chip gc; void __iomem *base; - spinlock_t lock; + raw_spinlock_t lock; unsigned long both_edges; }; @@ -74,9 +74,9 @@ static void ath79_gpio_irq_unmask(struct irq_data *data) u32 mask = BIT(irqd_to_hwirq(data)); unsigned long flags; - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); } static void ath79_gpio_irq_mask(struct irq_data *data) @@ -85,9 +85,9 @@ static void ath79_gpio_irq_mask(struct irq_data *data) u32 mask = BIT(irqd_to_hwirq(data)); unsigned long flags; - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); } static void ath79_gpio_irq_enable(struct irq_data *data) @@ -96,10 +96,10 @@ static void ath79_gpio_irq_enable(struct irq_data *data) u32 mask = BIT(irqd_to_hwirq(data)); unsigned long flags; - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); } static void ath79_gpio_irq_disable(struct irq_data *data) @@ -108,10 +108,10 @@ static void ath79_gpio_irq_disable(struct irq_data *data) u32 mask = BIT(irqd_to_hwirq(data)); unsigned long flags; - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); } static int ath79_gpio_irq_set_type(struct irq_data *data, @@ -140,7 +140,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *data, return -EINVAL; } - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); if (flow_type == IRQ_TYPE_EDGE_BOTH) { ctrl->both_edges |= mask; @@ -165,7 +165,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *data, ath79_gpio_update_bits( ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); return 0; } @@ -191,7 +191,7 @@ static void ath79_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irqchip, desc); - spin_lock_irqsave(&ctrl->lock, flags); + raw_spin_lock_irqsave(&ctrl->lock, flags); pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); @@ -203,7 +203,7 @@ static void ath79_gpio_irq_handler(struct irq_desc *desc) both_edges, ~state); } - spin_unlock_irqrestore(&ctrl->lock, flags); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); if (pending) { for_each_set_bit(irq, &pending, gc->ngpio) @@ -262,7 +262,7 @@ static int ath79_gpio_probe(struct platform_device *pdev) if (!ctrl->base) return -ENOMEM; - spin_lock_init(&ctrl->lock); + raw_spin_lock_init(&ctrl->lock); err = bgpio_init(&ctrl->gc, &pdev->dev, 4, ctrl->base + AR71XX_GPIO_REG_IN, ctrl->base + AR71XX_GPIO_REG_SET, -- 2.11.1