Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753404AbdCMOTQ (ORCPT ); Mon, 13 Mar 2017 10:19:16 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10101 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752851AbdCMOTG (ORCPT ); Mon, 13 Mar 2017 10:19:06 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 Mar 2017 07:19:00 -0700 Date: Mon, 13 Mar 2017 16:18:50 +0200 From: Peter De Schrijver To: Jon Hunter CC: Geert Uytterhoeven , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , "Thierry Reding" , Alexandre Courbot , linux-clk , , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Message-ID: <20170313141850.GX26640@tbergstrom-lnx.Nvidia.com> References: <4cf40c25-2ce9-737c-9ccb-06bc2cdb61d7@nvidia.com> <20170306083835.GF26640@tbergstrom-lnx.Nvidia.com> <6d4dd315-cab6-189d-f383-fb7523fc31bd@nvidia.com> <20170306142850.GJ26640@tbergstrom-lnx.Nvidia.com> <313f1245-02aa-496c-3545-5029ece652af@nvidia.com> <20170313104532.GT26640@tbergstrom-lnx.Nvidia.com> <9e81c653-b6bb-a47c-8891-d7c7d42a7650@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <9e81c653-b6bb-a47c-8891-d7c7d42a7650@nvidia.com> X-NVConfidentiality: public User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: DRUKMAIL101.nvidia.com (10.25.59.19) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2400 Lines: 59 On Mon, Mar 13, 2017 at 11:03:27AM +0000, Jon Hunter wrote: > > On 13/03/17 10:45, Peter De Schrijver wrote: > > On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote: > >> > >> On 08/03/17 11:38, Geert Uytterhoeven wrote: > >>> Hi Jon, > >>> > >>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter wrote: > >>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing > >>>>> the JTAG interface is powered down. > >>>> > >>>> This reminds me, does your patch assume that the DFD power domain is > >>>> enabled? I am guessing that it needs to be for JTAG to work. > >>> > >>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and > >>> marks the corresponding PM Domain as always-on, as long as the > >>> Coresight code doesn't handle runtime PM. > >> > >> Sorry Geert, but I was asking Peter specifically about the power-domain > >> on Tegra as I have a feeling we may have the same scenario ;-) > > > > We don't have a specific power domain for DFD on Tegra210. It's part of the > > non-powergateable core domain. > > Either we are getting our wires crossed or the TRM is wrong :-( > > static const char * const tegra210_powergates[] = { > [TEGRA_POWERGATE_CPU] = "crail", > [TEGRA_POWERGATE_3D] = "3d", > [TEGRA_POWERGATE_VENC] = "venc", > [TEGRA_POWERGATE_PCIE] = "pcie", > [TEGRA_POWERGATE_MPE] = "mpe", > [TEGRA_POWERGATE_SATA] = "sata", > [TEGRA_POWERGATE_CPU1] = "cpu1", > [TEGRA_POWERGATE_CPU2] = "cpu2", > [TEGRA_POWERGATE_CPU3] = "cpu3", > [TEGRA_POWERGATE_CPU0] = "cpu0", > [TEGRA_POWERGATE_C0NC] = "c0nc", > [TEGRA_POWERGATE_SOR] = "sor", > [TEGRA_POWERGATE_DIS] = "dis", > [TEGRA_POWERGATE_DISB] = "disb", > [TEGRA_POWERGATE_XUSBA] = "xusba", > [TEGRA_POWERGATE_XUSBB] = "xusbb", > [TEGRA_POWERGATE_XUSBC] = "xusbc", > [TEGRA_POWERGATE_VIC] = "vic", > [TEGRA_POWERGATE_IRAM] = "iram", > [TEGRA_POWERGATE_NVDEC] = "nvdec", > [TEGRA_POWERGATE_NVJPG] = "nvjpg", > [TEGRA_POWERGATE_AUD] = "aud", > [TEGRA_POWERGATE_DFD] = "dfd", > [TEGRA_POWERGATE_VE2] = "ve2", > }; > This seems to exist indeed. However downstream has never used it, so I wonder how well powergating this domain has been tested. Peter.