Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753899AbdCOO3B (ORCPT ); Wed, 15 Mar 2017 10:29:01 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:13099 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752561AbdCOO2c (ORCPT ); Wed, 15 Mar 2017 10:28:32 -0400 From: To: Michael Turquette , Stephen Boyd , Maxime Coquelin , Alexandre Torgue , Nicolas Pitre , Arnd Bergmann , , , CC: , , , Subject: [PATCH 0/2] STM32F4 clock fixes Date: Wed, 15 Mar 2017 15:27:49 +0100 Message-ID: <1489588071-18164-1-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-03-15_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 501 Lines: 15 From: Gabriel Fernandez This patch-set contains 2 fixes. One concerning exclusion of wrong values for PLLQ (0 & 1) And the second is a fix about timeout management of PLL and LSE/LSI clocks. Gabriel Fernandez (2): clk: stm32f4: fix: exclude values 0 and 1 for PLLQ clk: stm32f4: fix timeout management for pll and ready gate drivers/clk/clk-stm32f4.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) -- 1.9.1