Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751369AbdCPCld (ORCPT ); Wed, 15 Mar 2017 22:41:33 -0400 Received: from mail-sn1nam01on0048.outbound.protection.outlook.com ([104.47.32.48]:6479 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750788AbdCPClb (ORCPT ); Wed, 15 Mar 2017 22:41:31 -0400 From: "Zhang, Jerry" To: Alex Deucher CC: =?utf-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , "Zhou, David(ChunMing)" , Ayyappa Ch , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "platform-driver-x86@vger.kernel.org" , "helgaas@kernel.org" , "amd-gfx@lists.freedesktop.org" Subject: RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Thread-Topic: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access Thread-Index: AQHSm/cx6Mr4sRAenk2D3xgMnS9WW6GVgjsAgAAD2ICAAA16gIAAEcOAgAEZaCCAAAJoAIAABEmg Date: Thu, 16 Mar 2017 02:41:07 +0000 Message-ID: References: <1489408896-25039-1-git-send-email-deathsimple@vodafone.de> <1489408896-25039-5-git-send-email-deathsimple@vodafone.de> <6fac05e4-26ae-e959-9af6-cb68a04a1110@vodafone.de> <17c470c4-d406-b5ac-73d1-4dd5b83cfca8@vodafone.de> In-Reply-To: Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=amd.com; x-originating-ip: [116.228.147.241] x-microsoft-exchange-diagnostics: 1;MWHPR1201MB0208;7:42NeCWWv4c4hgWVRAqjduP0bIWS805wL7bI5OWvXvz+c6RePYFdGjpdPUIEiMFBiFZqtHFyFtcz0bWDy/qk+Vp0Nqz/8zWzFU7UReNxH7r8nQIa9tXAZkJ3lnMiA/ryUMPMXSyxjQZmUBckLqa922djQNyIdFviafGNeNAA1ZGYrb6OXdpH1iBuD9vicbfH1ajHEM+j+5rrzTcKZJcpKizahdsLshQGIgN7yg2+PrkFD+2qshRjUl6r+Adkx8Pl/uvYxdRE0hXlsxIHg+u0rC/XeeCCjbyS5vJ33Yhmz3yqxe3oxqhLXdgxuRFDhNKPc2S8N8vlHgWw6NJxNx5KOug==;20:r+wfeud8/z7oUrAOknqpdEwm6RQNvA38QQ39yG2DHeabckMf/Ob6vlRzPU6RQXlRDbPUR9pP8MJ6f0gh8RT4eftpNpeBQJsQMpQw94RGTtFPytWOKDvSs3ihWu2WdK2dbIv74/erjTmLKhxK4qKx4lADME7GjfUTk7a1C/E6BfEsOFaCyN/RiWYHdu4mpXY3vwadD5qXP29BTLReW1uZjYFCRJRCs7muUYRHmXg8+KPEG96OHTf1bmT6FTMTOhAv x-forefront-antispam-report: SFV:SKI;SCL:-1SFV:NSPM;SFS:(10009020)(6009001)(39860400002)(39840400002)(39450400003)(39850400002)(39410400002)(377454003)(24454002)(13464003)(189998001)(3846002)(6436002)(55016002)(3280700002)(33656002)(5660300001)(76176999)(2906002)(53936002)(6246003)(25786008)(2950100002)(9686003)(50986999)(8676002)(77096006)(99286003)(2900100001)(102836003)(1411001)(53546007)(66066001)(6916009)(54356999)(6116002)(6506006)(93886004)(3660700001)(110136004)(8936002)(229853002)(305945005)(86362001)(97736004)(54906002)(4326008)(7696004)(7736002)(122556002)(81166006)(6306002)(39060400002)(74316002)(38730400002)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR1201MB0208;H:DM5PR12MB1818.namprd12.prod.outlook.com;FPR:;SPF:None;MLV:ovrnspm;PTR:InfoNoRecords;LANG:en; x-ms-office365-filtering-correlation-id: c9e63bd4-7ea8-448e-639b-08d46c15e5ea x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(48565401081);SRVR:MWHPR1201MB0208; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(767451399110)(217544274631240); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040375)(601004)(2401047)(8121501046)(5005006)(3002001)(10201501046)(6055026)(6041248)(20161123564025)(20161123560025)(20161123562025)(20161123555025)(20161123558025)(6072148);SRVR:MWHPR1201MB0208;BCL:0;PCL:0;RULEID:;SRVR:MWHPR1201MB0208; x-forefront-prvs: 024847EE92 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Mar 2017 02:41:07.1577 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0208 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v2G2fhQ1009901 Content-Length: 9607 Lines: 236 Thanks for your info. I see. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _____________________________________ > -----Original Message----- > From: Alex Deucher [mailto:alexdeucher@gmail.com] > Sent: Thursday, March 16, 2017 10:25 > To: Zhang, Jerry > Cc: Christian König; Zhou, David(ChunMing); Ayyappa Ch; linux- > pci@vger.kernel.org; linux-kernel@vger.kernel.org; dri- > devel@lists.freedesktop.org; platform-driver-x86@vger.kernel.org; > helgaas@kernel.org; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > > On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: > >> -----Original Message----- > >> From: dri-devel [mailto:dri-devel-bounces@lists.freedesktop.org] On > >> Behalf Of Christian K?nig > >> Sent: Wednesday, March 15, 2017 17:29 > >> To: Zhou, David(ChunMing); Ayyappa Ch > >> Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; amd- > >> gfx@lists.freedesktop.org; platform-driver-x86@vger.kernel.org; > >> helgaas@kernel.org; dri-devel@lists.freedesktop.org > >> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > >> Yes, exactly that. > > > > (I'm not familiar with PCI too much.) > > Is there any restrict for PCI device? > > I'm concerning if any PCI couldn't support it on some motherboard. > > It depends on the PCI root bridge. This patch set only implements support for > AMD root bridges. Intel and other vendors would need similar code. > > Alex > > > > >> > >> Christian. > >> > >> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): > >> > Does that means we don't need invisible vram later? > >> > > >> > David > >> > > >> > -----Original Message----- > >> > From: dri-devel [mailto:dri-devel-bounces@lists.freedesktop.org] On > >> > Behalf Of Christian K?nig > >> > Sent: Wednesday, March 15, 2017 3:38 PM > >> > To: Ayyappa Ch > >> > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; > >> > amd-gfx@lists.freedesktop.org; platform-driver-x86@vger.kernel.org; > >> > helgaas@kernel.org; dri-devel@lists.freedesktop.org > >> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > > >> > Carizzo is an APU and resizing BARs isn't needed nor supported there. > >> > The CPU can access the full stolen VRAM directly on that hardware. > >> > > >> > As far as I know ASICs with support for this are Tonga, Fiji and all Polaris > variants. > >> > > >> > Christian. > >> > > >> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: > >> >> Is it possible on Carrizo asics? Or only supports on newer asics? > >> >> > >> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König > >> >> wrote: > >> >>> From: Christian König > >> >>> > >> >>> Try to resize BAR0 to let CPU access all of VRAM. > >> >>> > >> >>> Signed-off-by: Christian König > >> >>> --- > >> >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > >> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 > >> +++++++++++++++++++++++++++++ > >> >>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +++++--- > >> >>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +++++--- > >> >>> 4 files changed, 40 insertions(+), 6 deletions(-) > >> >>> > >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> index 3b81ded..905ded9 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct > >> amdgpu_device *adev, struct ttm_tt *ttm, > >> >>> struct ttm_mem_reg *mem); > >> >>> void amdgpu_vram_location(struct amdgpu_device *adev, struct > >> amdgpu_mc *mc, u64 base); > >> >>> void amdgpu_gtt_location(struct amdgpu_device *adev, struct > >> >>> amdgpu_mc *mc); > >> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev); > >> >>> void amdgpu_ttm_set_active_vram_size(struct amdgpu_device > >> >>> *adev, > >> u64 size); > >> >>> int amdgpu_ttm_init(struct amdgpu_device *adev); > >> >>> void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git > >> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> >>> index 118f4e6..92955fe 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> >>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct > >> >>> amdgpu_device > >> *adev, struct amdgpu_mc *mc) > >> >>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); > >> >>> } > >> >>> > >> >>> +/** > >> >>> + * amdgpu_resize_bar0 - try to resize BAR0 > >> >>> + * > >> >>> + * @adev: amdgpu_device pointer > >> >>> + * > >> >>> + * Try to resize BAR0 to make all VRAM CPU accessible. > >> >>> + */ > >> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev) { > >> >>> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20; > >> >>> + int r; > >> >>> + > >> >>> + r = pci_resize_resource(adev->pdev, 0, size); > >> >>> + > >> >>> + if (r == -ENOTSUPP) { > >> >>> + /* The hardware don't support the extension. */ > >> >>> + return; > >> >>> + > >> >>> + } else if (r == -ENOSPC) { > >> >>> + DRM_INFO("Not enoigh PCI address space for a large BAR."); > >> >>> + } else if (r) { > >> >>> + DRM_ERROR("Problem resizing BAR0 (%d).", r); > >> >>> + } > >> >>> + > >> >>> + /* Reinit the doorbell mapping, it is most likely moved as well */ > >> >>> + amdgpu_doorbell_fini(adev); > >> >>> + BUG_ON(amdgpu_doorbell_init(adev)); > >> >>> +} > >> >>> + > >> >>> /* > >> >>> * GPU helpers function. > >> >>> */ > >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > >> >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > >> >>> index dc9b6d6..36a7aa5 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > >> >>> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct > >> >>> amdgpu_device > >> *adev) > >> >>> break; > >> >>> } > >> >>> adev->mc.vram_width = numchan * chansize; > >> >>> - /* Could aper size report 0 ? */ > >> >>> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); > >> >>> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); > >> >>> /* size in MB on si */ > >> >>> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * > >> >>> 1024ULL * > >> 1024ULL; > >> >>> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * > >> >>> 1024ULL > >> >>> * 1024ULL; > >> >>> > >> >>> + if (!(adev->flags & AMD_IS_APU)) > >> >>> + amdgpu_resize_bar0(adev); > >> >>> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); > >> >>> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); > >> >>> + > >> >>> #ifdef CONFIG_X86_64 > >> >>> if (adev->flags & AMD_IS_APU) { > >> >>> adev->mc.aper_base = > >> >>> ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; diff --git > >> >>> a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > >> >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > >> >>> index c087b00..7761ad3 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > >> >>> @@ -459,13 +459,15 @@ static int gmc_v8_0_mc_init(struct > >> >>> amdgpu_device > >> *adev) > >> >>> break; > >> >>> } > >> >>> adev->mc.vram_width = numchan * chansize; > >> >>> - /* Could aper size report 0 ? */ > >> >>> - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); > >> >>> - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); > >> >>> /* size in MB on si */ > >> >>> adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * > >> >>> 1024ULL * > >> 1024ULL; > >> >>> adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * > >> >>> 1024ULL > >> >>> * 1024ULL; > >> >>> > >> >>> + if (!(adev->flags & AMD_IS_APU)) > >> >>> + amdgpu_resize_bar0(adev); > >> >>> + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); > >> >>> + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); > >> >>> + > >> >>> #ifdef CONFIG_X86_64 > >> >>> if (adev->flags & AMD_IS_APU) { > >> >>> adev->mc.aper_base = > >> >>> ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; > >> >>> -- > >> >>> 2.7.4 > >> >>> > >> >>> _______________________________________________ > >> >>> dri-devel mailing list > >> >>> dri-devel@lists.freedesktop.org > >> >>> https://lists.freedesktop.org/mailman/listinfo/dri-devel > >> > > >> > _______________________________________________ > >> > dri-devel mailing list > >> > dri-devel@lists.freedesktop.org > >> > https://lists.freedesktop.org/mailman/listinfo/dri-devel > >> > _______________________________________________ > >> > amd-gfx mailing list > >> > amd-gfx@lists.freedesktop.org > >> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >> > >> > >> _______________________________________________ > >> dri-devel mailing list > >> dri-devel@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx