Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751829AbdCPIRg (ORCPT ); Thu, 16 Mar 2017 04:17:36 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:32358 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751281AbdCPIRc (ORCPT ); Thu, 16 Mar 2017 04:17:32 -0400 From: To: Michael Turquette , Stephen Boyd , Maxime Coquelin , Alexandre Torgue , Nicolas Pitre , Arnd Bergmann , , , CC: , , , Subject: [PATCH v2 0/2] STM32F4 clock fixes Date: Thu, 16 Mar 2017 09:16:39 +0100 Message-ID: <1489652201-19889-1-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG3NODE3.st.com (10.75.127.9) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-03-16_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 674 Lines: 21 From: Gabriel Fernandez v2: Just add "Fixes" tags. This patch-set contains 2 fixes. One concerning exclusion of wrong values for PLLQ (0 & 1) Fixes: 83135ad3c517 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards") And the second is a fix about timeout management of PLL and LSE/LSI clocks. Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks") Gabriel Fernandez (2): clk: stm32f4: fix: exclude values 0 and 1 for PLLQ clk: stm32f4: fix timeout management for pll and ready gate drivers/clk/clk-stm32f4.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) -- 1.9.1