Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752975AbdCPRK0 (ORCPT ); Thu, 16 Mar 2017 13:10:26 -0400 Received: from foss.arm.com ([217.140.101.70]:36958 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752174AbdCPRKY (ORCPT ); Thu, 16 Mar 2017 13:10:24 -0400 From: Andre Przywara To: Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/2] irqchip/gic-v3-its: LPI tables fixes Date: Thu, 16 Mar 2017 17:05:40 +0000 Message-Id: <20170316170542.3568-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 753 Lines: 22 By staring at the code (while writing the ITS driver for Xen) I stumbled upon two minor things that deserve fixing: Patch 1 checks whether LPIs are really disabled before setting up the tables, as the architecture actually disallows clearing the LPI enable bit. We try this anyway, but bail out if this fails. Patch 2 makes sure we don't miss when the redistributors denies our cacheable mapping request. Please have a look and apply if that makes sense. Cheers, Andre. Andre Przywara (2): irqchip/gic-v3-its: bail out on already enabled LPIs irqchip/gic-v3-its: always check for cacheability attributes drivers/irqchip/irq-gic-v3-its.c | 41 ++++++++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) -- 2.9.0