Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752431AbdCPSCj (ORCPT ); Thu, 16 Mar 2017 14:02:39 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11808 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751997AbdCPSCi (ORCPT ); Thu, 16 Mar 2017 14:02:38 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 16 Mar 2017 11:02:27 -0700 Subject: Re: [PATCH 1/2] mmc: sdhci: Add support for setting parent clock To: Adrian Hunter , Ulf Hansson , Thierry Reding , "Ritesh Harjani" References: <1489660364-17698-1-git-send-email-jonathanh@nvidia.com> CC: , , From: Jon Hunter Message-ID: <6072f40f-78e1-9c7a-6c9a-8db99f771af1@nvidia.com> Date: Thu, 16 Mar 2017 18:00:00 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <1489660364-17698-1-git-send-email-jonathanh@nvidia.com> X-Originating-IP: [10.21.132.150] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1999 Lines: 50 On 16/03/17 10:32, Jon Hunter wrote: > It is common for SD/MMC host controllers to set the parent clock that > drives the SD/MMC interface in order to support various operating > speeds. Typically, this is performed by calling common clock framework > APIs such as clk_set_rate(). The problem is that these APIs may sleep > and must not be called from within atomic sections and therefore, these > functions cannot be called within the existing 'set_clock' SDHCI > operator because they are called from within the context of a spinlock. > Add a new 'set_parent_clock' operator for the SDHCI driver that is > called early during the SDHCI 'set_ios' before the spinlock is aquire to > give the platform driver the opportunity to set the parent clock rate. > > Please note that, unfortunately, the Tegra and MSM SDHCI drivers > currently appear to mis-use the 'set_clock' operator by calling > clk_set_rate(). In the case of Tegra, occasionally but not always, > 'scheduling while atomic' errors are reported (so most of the time we > are getting lucky). In the of the MSM SDHCI driver, it is releasing and > re-acquiring the spinlock which is bad. > > Signed-off-by: Jon Hunter > --- > > I have not attempted to fix the MSM driver in this seris, but I am > copying hopefully, the right people to fix it. > > drivers/mmc/host/sdhci.c | 3 +++ > drivers/mmc/host/sdhci.h | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 6fdd7a70f229..b7f1521edbec 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1579,6 +1579,9 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > if (ios->power_mode == MMC_POWER_UNDEFINED) > return; > > + if (host->ops->set_parent_clock) > + host->ops->set_parent_clock(host, ios->power_mode); Ugh ... not sure what happened here but this should be 'ios->clock'! And I did test this! Sorry will resend. Jon -- nvpublic