Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752358AbdCQB3Q (ORCPT ); Thu, 16 Mar 2017 21:29:16 -0400 Received: from regular1.263xmail.com ([211.150.99.133]:52102 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751098AbdCQB3L (ORCPT ); Thu, 16 Mar 2017 21:29:11 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: mark.yao@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <4b672fb4a5a85e2e35217991a81bdfed> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 To: John Keeping References: <1489635107-21327-1-git-send-email-zyw@rock-chips.com> <1489635107-21327-2-git-send-email-zyw@rock-chips.com> <20170316105500.675b413f.john@metanate.com> Cc: linux-rockchip@lists.infradead.org, Heiko Stuebner , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, Mark Yao From: Chris Zhong Message-ID: <58CB398A.9050800@rock-chips.com> Date: Fri, 17 Mar 2017 09:19:06 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170316105500.675b413f.john@metanate.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1712 Lines: 55 Hi John On 03/16/2017 06:55 PM, John Keeping wrote: > On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote: > >> For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is >> disabled, MIPI phy can not work. Let's return a error if there is no >> phy_cfg_clk in dts property, when the pdata match RK3399. >> >> Signed-off-by: Chris Zhong >> --- >> >> Changes in v2: None >> >> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++------ >> 1 file changed, 4 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c >> index f84f9ae..11c4166 100644 >> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c >> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c >> @@ -1227,15 +1227,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, >> clk_disable_unprepare(dsi->pclk); >> } >> >> - dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); >> - if (IS_ERR(dsi->phy_cfg_clk)) { >> - ret = PTR_ERR(dsi->phy_cfg_clk); >> - if (ret != -ENOENT) { >> + if (pdata == &rk3399_mipi_dsi_drv_data) { > This will get messy if the next SOC also needs phy_cfg_clk. Can we do > something like: > > if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { > ... Thanks, good idea. I think RK3368 mipi-dsi driver is on the way. :) >> + dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); >> + if (IS_ERR(dsi->phy_cfg_clk)) { >> + ret = PTR_ERR(dsi->phy_cfg_clk); >> dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret); >> return ret; >> } >> - dsi->phy_cfg_clk = NULL; >> - dev_dbg(dev, "have not phy_cfg_clk\n"); >> } >> >> ret = clk_prepare_enable(dsi->pllref_clk); > > -- Chris Zhong