Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbdCRTFC (ORCPT ); Sat, 18 Mar 2017 15:05:02 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:56865 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751695AbdCRTE7 (ORCPT ); Sat, 18 Mar 2017 15:04:59 -0400 X-Auth-Info: 9Gb8ZGbUc6dyvlLpuej/+czKAJ7R87OSECHqxbEnJtc= Date: Sat, 18 Mar 2017 19:53:56 +0100 From: Anatolij Gustschin To: matthew.gerlach@linux.intel.com Cc: atull@kernel.org, moritz.fischer@ettus.com, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. Message-ID: <20170318195356.19269415@crub> In-Reply-To: <1489174827-6033-3-git-send-email-matthew.gerlach@linux.intel.com> References: <1489174827-6033-1-git-send-email-matthew.gerlach@linux.intel.com> <1489174827-6033-3-git-send-email-matthew.gerlach@linux.intel.com> X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1528 Lines: 67 Hi Matthew, thanks for the patches. Please see some comments below. On Fri, 10 Mar 2017 11:40:25 -0800 matthew.gerlach@linux.intel.com matthew.gerlach@linux.intel.com wrote: ... >+ if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { >+ pr_err("%s Partial Reconfiguration flag not set\n", __func__); please use dev_err() here. ... >+ if (val & ALT_PR_CSR_PR_START) { >+ pr_err("%s Partial Reconfiguration already started\n", dev_err(), too. ... >+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr, >+ struct fpga_image_info *info) >+{ >+ u32 i; >+ >+ for (i = 0; i < info->config_complete_timeout_us; i++) { >+ switch (alt_pr_fpga_state(mgr)) { >+ case FPGA_MGR_STATE_WRITE_ERR: >+ return -EIO; >+ >+ case FPGA_MGR_STATE_OPERATING: >+ dev_info(&mgr->dev, >+ "successful partial reconfiguration\n"); >+ return 0; >+ >+ default: >+ break; >+ } >+ udelay(1); >+ } >+ dev_err(&mgr->dev, "timed out waiting for write to complete\n"); >+ return -ETIMEDOUT; >+} we will always get timed out error if info->config_complete_timeout_us is zero. Can we change to u32 i = 0; ... do { ... } while (info->config_complete_timeout_us > i++); ? ... >diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h >new file mode 100644 >index 0000000..3810a90 >--- /dev/null >+++ b/drivers/fpga/altera-pr-ip-core.h Should we move this header to include/linux/? We can use register/ unregister functions in other drivers (PCIe) outside drivers/fpga then. Thanks, Anatolij