Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbdCTCvr (ORCPT ); Sun, 19 Mar 2017 22:51:47 -0400 Received: from mail-cys01nam02on0064.outbound.protection.outlook.com ([104.47.37.64]:58816 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751966AbdCTCvo (ORCPT ); Sun, 19 Mar 2017 22:51:44 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; From: Yuantian Tang To: CC: , , , , , , , Scott Wood , Tang Yuantian Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Date: Mon, 20 Mar 2017 10:37:22 +0800 Message-ID: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131344519005840574;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(336005)(39380400002)(39840400002)(39400400002)(39410400002)(39450400003)(39860400002)(39850400002)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(9170700003)(53936002)(110136004)(47776003)(5660300001)(104016004)(50226002)(8676002)(48376002)(5003940100001)(4326008)(54906002)(6916009)(305945005)(81166006)(7416002)(50466002)(2906002)(356003)(36756003)(86362001)(105606002)(106466001)(50986999)(33646002)(6666003)(38730400002)(8656002)(2351001)(8936002)(189998001)(77096006)(85426001);DIR:OUT;SFP:1101;SCL:1;SRVR:MWHPR03MB2798;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:ovrnspm;MX:1;A:1;PTR:InfoDomainNonexistent;LANG:en; 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Update the qoriq-clock binding to allow a second input clock, named "coreclk". If present, this clock will be used for the core PLLs. Signed-off-by: Scott Wood Signed-off-by: Tang Yuantian Acked-by: Rob Herring --- v2: -- change the author to Scott Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index aa3526f..119cafd 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -56,6 +56,11 @@ Optional properties: - clocks: If clock-frequency is not specified, sysclk may be provided as an input clock. Either clock-frequency or clocks must be provided. + A second input clock, called "coreclk", may be provided if + core PLLs are based on a different input clock from the + platform PLL. +- clock-names: Required if a coreclk is present. Valid names are + "sysclk" and "coreclk". 2. Clock Provider @@ -72,6 +77,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 5 coreclk must be 0 3. Example -- 2.1.0.27.g96db324