Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754839AbdCTMnL (ORCPT ); Mon, 20 Mar 2017 08:43:11 -0400 Received: from mail-wm0-f42.google.com ([74.125.82.42]:36000 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754779AbdCTMnJ (ORCPT ); Mon, 20 Mar 2017 08:43:09 -0400 Date: Mon, 20 Mar 2017 20:10:46 +0800 From: Leo Yan To: Suzuki K Poulose Cc: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, sudeep.holla@arm.com Subject: Re: [PATCH v4 4/7] coresight: add support for CPU debug module Message-ID: <20170320121046.GB19581@leoy-linaro> References: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> <1489762943-25849-5-git-send-email-leo.yan@linaro.org> <74d6fd19-89f0-7edf-ace3-8b07f13e9569@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <74d6fd19-89f0-7edf-ace3-8b07f13e9569@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1901 Lines: 44 On Fri, Mar 17, 2017 at 06:44:03PM +0000, Suzuki K Poulose wrote: > On 17/03/17 15:02, Leo Yan wrote: > >Coresight includes debug module and usually the module connects with CPU > >debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has > >description for related info in "Part H: External Debug". > > > >Chapter H7 "The Sample-based Profiling Extension" introduces several > >sampling registers, e.g. we can check program counter value with > >combined CPU exception level, secure state, etc. So this is helpful for > >analysis CPU lockup scenarios, e.g. if one CPU has run into infinite > >loop with IRQ disabled. In this case the CPU cannot switch context and > >handle any interrupt (including IPIs), as the result it cannot handle > >SMP call for stack dump. > > > >This patch is to enable coresight debug module, so firstly this driver > >is to bind apb clock for debug module and this is to ensure the debug > >module can be accessed from program or external debugger. And the driver > >uses sample-based registers for debug purpose, e.g. when system detects > >the CPU lockup and trigger panic, the driver will dump program counter > > Do we dump it when the CPU lockup is detected with this change ? If not, > we shouldn't claim that here. Right, the mainline kernel missed Colin Cross's patch to trigger panic when detect CPU lockup which used by Android common kernel: http://people.linaro.org/~leo.yan/0001-hardlockup-detect-hard-lockups-without-NMIs-using-se.patch Will fix it. [...] > >+ pr_emerg("\tEDPCSR: [<%p>] %pS\n", (void *)pc, (void *)pc); > > Are we safe calling %pS on the PC, when the PC offset in implementation defined ? I did some quick testing, if cannot find proper kernel symbol for PC value, then %pS will directly output pc value rather than symbol value. Other suggestions are good for me; I will fix for all for them. [...] Thanks, Leo Yan