Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755699AbdCTQef (ORCPT ); Mon, 20 Mar 2017 12:34:35 -0400 Received: from terminus.zytor.com ([65.50.211.136]:55886 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753311AbdCTQea (ORCPT ); Mon, 20 Mar 2017 12:34:30 -0400 Date: Mon, 20 Mar 2017 09:31:02 -0700 From: tip-bot for Kyle Huey Message-ID: Cc: grzegorz.andrejczuk@intel.com, rkrcmar@redhat.com, andi@firstfloor.org, me@kylehuey.com, linux-kernel@vger.kernel.org, peterz@infradead.org, dave.hansen@linux.intel.com, pbonzini@redhat.com, richard@nod.at, dsafonov@virtuozzo.com, luto@kernel.org, tglx@linutronix.de, nadav.amit@gmail.com, shuah@kernel.org, dmatlack@google.com, bp@suse.de, boris.ostrovsky@oracle.com, viro@zeniv.linux.org.uk, hpa@zytor.com, len.brown@intel.com, mingo@kernel.org, robert@ocallahan.org, khuey@kylehuey.com, jdike@addtoit.com, rafael.j.wysocki@intel.com Reply-To: luto@kernel.org, tglx@linutronix.de, richard@nod.at, dsafonov@virtuozzo.com, peterz@infradead.org, dave.hansen@linux.intel.com, pbonzini@redhat.com, grzegorz.andrejczuk@intel.com, me@kylehuey.com, andi@firstfloor.org, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, khuey@kylehuey.com, rafael.j.wysocki@intel.com, jdike@addtoit.com, robert@ocallahan.org, mingo@kernel.org, hpa@zytor.com, len.brown@intel.com, boris.ostrovsky@oracle.com, viro@zeniv.linux.org.uk, dmatlack@google.com, bp@suse.de, nadav.amit@gmail.com, shuah@kernel.org In-Reply-To: <20170320081628.18952-2-khuey@kylehuey.com> References: <20170320081628.18952-2-khuey@kylehuey.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/process] x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES Git-Commit-ID: ab6d9468631a6e56e4c071c6ce6710956485fe08 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3305 Lines: 86 Commit-ID: ab6d9468631a6e56e4c071c6ce6710956485fe08 Gitweb: http://git.kernel.org/tip/ab6d9468631a6e56e4c071c6ce6710956485fe08 Author: Kyle Huey AuthorDate: Mon, 20 Mar 2017 01:16:19 -0700 Committer: Thomas Gleixner CommitDate: Mon, 20 Mar 2017 16:10:32 +0100 x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES This matches the only public Intel documentation of this MSR, in the "Virtualization Technology FlexMigration Application Note" (preserved at https://bugzilla.kernel.org/attachment.cgi?id=243991) Signed-off-by: Kyle Huey Cc: Grzegorz Andrejczuk Cc: kvm@vger.kernel.org Cc: Radim Krčmář Cc: Peter Zijlstra Cc: Dave Hansen Cc: Andi Kleen Cc: linux-kselftest@vger.kernel.org Cc: Nadav Amit Cc: Robert O'Callahan Cc: Richard Weinberger Cc: "Rafael J. Wysocki" Cc: Borislav Petkov Cc: Andy Lutomirski Cc: Len Brown Cc: Shuah Khan Cc: user-mode-linux-devel@lists.sourceforge.net Cc: Jeff Dike Cc: Alexander Viro Cc: user-mode-linux-user@lists.sourceforge.net Cc: David Matlack Cc: Boris Ostrovsky Cc: Dmitry Safonov Cc: linux-fsdevel@vger.kernel.org Cc: Paolo Bonzini Link: http://lkml.kernel.org/r/20170320081628.18952-2-khuey@kylehuey.com Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msr-index.h | 6 +++--- arch/x86/kernel/cpu/intel.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4c928f3..f429b70 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -553,10 +553,10 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) -/* MISC_FEATURE_ENABLES non-architectural features */ -#define MSR_MISC_FEATURE_ENABLES 0x00000140 +/* MISC_FEATURES_ENABLES non-architectural features */ +#define MSR_MISC_FEATURES_ENABLES 0x00000140 -#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 +#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 #define MSR_IA32_TSC_DEADLINE 0x000006E0 diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 0631977..e229318 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -91,13 +91,13 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) } if (ring3mwait_disabled) { - msr_clear_bit(MSR_MISC_FEATURE_ENABLES, - MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); + msr_clear_bit(MSR_MISC_FEATURES_ENABLES, + MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); return; } - msr_set_bit(MSR_MISC_FEATURE_ENABLES, - MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); + msr_set_bit(MSR_MISC_FEATURES_ENABLES, + MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); set_cpu_cap(c, X86_FEATURE_RING3MWAIT);