Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755836AbdCTQfa (ORCPT ); Mon, 20 Mar 2017 12:35:30 -0400 Received: from terminus.zytor.com ([65.50.211.136]:56062 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755819AbdCTQfZ (ORCPT ); Mon, 20 Mar 2017 12:35:25 -0400 Date: Mon, 20 Mar 2017 09:34:22 -0700 From: tip-bot for Kyle Huey Message-ID: Cc: boris.ostrovsky@oracle.com, pbonzini@redhat.com, robert@ocallahan.org, khuey@kylehuey.com, me@kylehuey.com, viro@zeniv.linux.org.uk, andi@firstfloor.org, rafael.j.wysocki@intel.com, richard@nod.at, grzegorz.andrejczuk@intel.com, hpa@zytor.com, bp@suse.de, rkrcmar@redhat.com, tglx@linutronix.de, dsafonov@virtuozzo.com, dave.hansen@linux.intel.com, mingo@kernel.org, dmatlack@google.com, peterz@infradead.org, shuah@kernel.org, linux-kernel@vger.kernel.org, jdike@addtoit.com, luto@kernel.org, len.brown@intel.com, nadav.amit@gmail.com Reply-To: me@kylehuey.com, khuey@kylehuey.com, robert@ocallahan.org, boris.ostrovsky@oracle.com, pbonzini@redhat.com, andi@firstfloor.org, rafael.j.wysocki@intel.com, viro@zeniv.linux.org.uk, bp@suse.de, hpa@zytor.com, richard@nod.at, grzegorz.andrejczuk@intel.com, tglx@linutronix.de, rkrcmar@redhat.com, dmatlack@google.com, dsafonov@virtuozzo.com, mingo@kernel.org, dave.hansen@linux.intel.com, shuah@kernel.org, peterz@infradead.org, luto@kernel.org, jdike@addtoit.com, linux-kernel@vger.kernel.org, nadav.amit@gmail.com, len.brown@intel.com In-Reply-To: <20170320081628.18952-8-khuey@kylehuey.com> References: <20170320081628.18952-8-khuey@kylehuey.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/process] x86/cpufeature: Detect CPUID faulting support Git-Commit-ID: 90218ac77d0582eaf2d0872d8d900cbd5bf1f205 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4367 Lines: 121 Commit-ID: 90218ac77d0582eaf2d0872d8d900cbd5bf1f205 Gitweb: http://git.kernel.org/tip/90218ac77d0582eaf2d0872d8d900cbd5bf1f205 Author: Kyle Huey AuthorDate: Mon, 20 Mar 2017 01:16:25 -0700 Committer: Thomas Gleixner CommitDate: Mon, 20 Mar 2017 16:10:34 +0100 x86/cpufeature: Detect CPUID faulting support Intel supports faulting on the CPUID instruction beginning with Ivy Bridge. When enabled, the processor will fault on attempts to execute the CPUID instruction with CPL>0. This will allow a ptracer to emulate the CPUID instruction. Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is documented in detail in Section 2.3.2 of https://bugzilla.kernel.org/attachment.cgi?id=243991 Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT. Signed-off-by: Kyle Huey Reviewed-by: Borislav Petkov Cc: Grzegorz Andrejczuk Cc: kvm@vger.kernel.org Cc: Radim Krčmář Cc: Peter Zijlstra Cc: Dave Hansen Cc: Andi Kleen Cc: linux-kselftest@vger.kernel.org Cc: Nadav Amit Cc: Robert O'Callahan Cc: Richard Weinberger Cc: "Rafael J. Wysocki" Cc: Andy Lutomirski Cc: Len Brown Cc: Shuah Khan Cc: user-mode-linux-devel@lists.sourceforge.net Cc: Jeff Dike Cc: Alexander Viro Cc: user-mode-linux-user@lists.sourceforge.net Cc: David Matlack Cc: Boris Ostrovsky Cc: Dmitry Safonov Cc: linux-fsdevel@vger.kernel.org Cc: Paolo Bonzini Link: http://lkml.kernel.org/r/20170320081628.18952-8-khuey@kylehuey.com Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/intel.c | 24 +++++++++++++++++++++++- 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b04bb6d..0fe0044 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -187,6 +187,7 @@ * Reuse free bits when adding new feature flags! */ #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f429b70..b1f75da 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -45,6 +45,8 @@ #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce +#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 +#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e229318..a07f829 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -488,6 +488,28 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c) init_intel_energy_perf(c); } +static void init_cpuid_fault(struct cpuinfo_x86 *c) +{ + u64 msr; + + if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { + if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) + set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); + } +} + +static void init_intel_misc_features(struct cpuinfo_x86 *c) +{ + u64 msr; + + if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) + return; + + /* Check features and update capabilities */ + init_cpuid_fault(c); + probe_xeon_phi_r3mwait(c); +} + static void init_intel(struct cpuinfo_x86 *c) { unsigned int l2 = 0; @@ -602,7 +624,7 @@ static void init_intel(struct cpuinfo_x86 *c) init_intel_energy_perf(c); - probe_xeon_phi_r3mwait(c); + init_intel_misc_features(c); } #ifdef CONFIG_X86_32