Date: Tue, 21 Mar 2017 09:23:40 +0000
From: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
To: Tony Lindgren <tony@atomide.com>
CC: Mark Brown <broonie@kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-omap@vger.kernel.org>, Lee Jones <lee.jones@linaro.org>,
        Marcel Partap <mpartap@gmx.net>,
        Michael Scott <michael.scott@linaro.org>,
        "Sebastian Reichel" <sre@kernel.org>
Subject: Re: [PATCH 1/4] regmap: irq: Fix lost interrupts by introducing
 handle_reread
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 <20170320153341.GK20572@atomide.com>
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On Mon, Mar 20, 2017 at 08:33:42AM -0700, Tony Lindgren wrote:
> * Charles Keepax <ckeepax@opensource.wolfsonmicro.com> [170320 08:15]:
> > On Thu, Mar 16, 2017 at 05:36:30PM -0700, Tony Lindgren wrote:
> > > At least Motorola CPCAP PMIC needs it's device interrupts re-read
> > > until there are no more interrupts. Otherwise the PMIC interrupt to
> > > the SoC will eventually stop toggling.
> > > 
> > > Let's allow doing that by introducing a flag for handle_reread
> > > and by splitting regmap_irq_thread() into two separate functions
> > > for regmap_read_irq_status() and regmap_irq_handle_pending().
> > > 
> > 
> > Is this actually a property of this hardware or is this just a
> > result of connecting a device that generates level IRQs to a host
> > that is expecting an edge triggered IRQ?
> 
> Well the CPCAP PMIC interrupt is connected to a GPIO edge interrupt
> on the SoC in the Motorola v3.8 based kernel tree. But what the CPCAP
> PMIC interrupt handler does in the Motorola kernel is keep handling
> the CPCAP internal interrupts (and also keep reading the SoC GPIO
> line status!) until the GPIO line changes status. So yeah it's a
> property of the CPCAP PMIC hardware.
> 

That sounds a lot like a level triggered IRQ. If they are
repeatedly reading the GPIO line until it returns to high to know
they need to process more IRQs, that implies the line is staying
low whilst IRQs need handling which is level triggered.

> Changing the GPIO interrupt to level makes no difference here. It's
> not clear why they had marked the CPCAP PMIC to SoC GPIO interrupt
> as edge though in the Motorola kernel. My guess is that some PMIC
> to SoC wake-up events are edge interrupts. So we have it set up as
> edge interrupt in the mainline kernel too.
> 

I guess my only comment here is are we sure this isn't a bug in
supporting level IRQs in the GPIO driver, of course it could be
that the SoC simply doesn't support level IRQs that is fairly
common as well. But I guess we should be clear in the commit
message if this is adding emulation of level triggered IRQs and
possible add some gating on type of IRQ requested.

Thanks,
Charles