Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759544AbdCVMsq (ORCPT ); Wed, 22 Mar 2017 08:48:46 -0400 Received: from mail.integranet.hu ([185.80.49.33]:40378 "EHLO mail.integranet.hu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759122AbdCVMsX (ORCPT ); Wed, 22 Mar 2017 08:48:23 -0400 X-Greylist: delayed 1491 seconds by postgrey-1.27 at vger.kernel.org; Wed, 22 Mar 2017 08:48:22 EDT Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 10.2 \(3259\)) Subject: Re: [PATCH v3 0/7] ARM: Fix dma_alloc_coherent() and friends for NOMMU From: =?utf-8?B?U3plbXrFkSBBbmRyw6Fz?= In-Reply-To: <90e219f3-7139-c11c-a635-509173d4148a@arm.com> Date: Wed, 22 Mar 2017 13:23:26 +0100 Cc: linux-arm-kernel@lists.infradead.org, Mark Rutland , Roger Quadros , Joerg Roedel , alexandre.torgue@st.com, Yoshinori Sato , Greg Kroah-Hartman , linux@armlinux.org.uk, Michal Nazarewicz , linux-kernel@vger.kernel.org, Christian Borntraeger , Doug Ledford , Rich Felker , Alan Stern , kbuild-all@01.org, benjamin.gaignard@linaro.org, Rob Herring , akpm@linux-foundation.org, Marek Szyprowski , robin.murphy@arm.com Message-Id: <33321273-E3E7-459B-A615-5ADA52445AA1@esh.hu> References: <1489137839-549-1-git-send-email-vladimir.murzin@arm.com> <90e219f3-7139-c11c-a635-509173d4148a@arm.com> To: Vladimir Murzin X-Mailer: Apple Mail (2.3259) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v2MCn756031158 Content-Length: 4324 Lines: 106 I’ve tested this v3 version on my Atmel armv7m board with several drivers with DMA and enabled caches, and I’ve not seen any issues. You can add my Tested-by. Thanks for the patches! Andras > On 2017. Mar 16., at 10:03, Vladimir Murzin wrote: > > Gentle ping! > > On 10/03/17 09:23, Vladimir Murzin wrote: >> It seem that addition of cache support for M-class CPUs uncovered >> latent bug in DMA usage. NOMMU memory model has been treated as being >> always consistent; however, for R/M CPU classes memory can be covered >> by MPU which in turn might configure RAM as Normal i.e. bufferable and >> cacheable. It breaks dma_alloc_coherent() and friends, since data can >> stuck in caches now or be buffered. >> >> This patch set is trying to address the issue by providing region of >> memory suitable for consistent DMA operations. It is supposed that >> such region is marked by MPU as non-cacheable. Robin suggested to >> advertise such memory as reserved shared-dma-pool, rather then using >> homebrew command line option, and extend dma-coherent to provide >> default DMA area in the similar way as it is done for CMA (PATCH >> 4/7). It allows us to offload all bookkeeping on generic coherent DMA >> framework, and it seems that it might be reused by other architectures >> like c6x and blackfin. >> >> While reviewing/testing previous vesrions of the patch set it turned >> out that dma-coherent does not take into account "dma-ranges" device >> tree property, so it is addressed in PATCH 3/7. >> >> For ARM, dedicated DMA region is required for cases other than: >> - MMU/MPU is off >> - cpu is v7m w/o cache support >> - device is coherent >> >> In case one of the above conditions is true dma operations are forced >> to be coherent and wired with dma_noop_ops. >> >> To make life easier NOMMU dma operations are kept in separate >> compilation unit. >> >> Since the issue was reported in the same time as Benjamin sent his >> patch [1] to allow mmap for NOMMU, his case is also addressed in this >> series (PATCH 1/7 and PATCH 2/7). >> >> Thanks! >> >> [1] http://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8633/1 >> >> Cc: Joerg Roedel >> Cc: Christian Borntraeger >> Cc: Michal Nazarewicz >> Cc: Marek Szyprowski >> Cc: Alan Stern >> Cc: Yoshinori Sato >> Cc: Rich Felker >> Cc: Roger Quadros >> Cc: Greg Kroah-Hartman >> Cc: Rob Herring >> Cc: Mark Rutland >> Cc: Doug Ledford >> >> Changelog: >> v2 -> v3 >> - fixed warnings reported by Alexandre and kbuild robot >> >> v1 -> v2 >> - rebased on v4.11-rc1 >> - added Robin's Reviewed-by >> - dedicated flag is introduced to use dev->dma_pfn_offset >> rather than mem->device_base in case memory region is >> configured via device tree (so Tested-by discarded there) >> >> RFC v6 -> v1 >> - dropped RFC tag >> - added Alexandre's Tested-by >> >> Vladimir Murzin (7): >> dma: Take into account dma_pfn_offset >> dma: Add simple dma_noop_mmap >> drivers: dma-coherent: Account dma_pfn_offset when used with device >> tree >> drivers: dma-coherent: Introduce default DMA pool >> ARM: NOMMU: Introduce dma operations for noMMU >> ARM: NOMMU: Set ARM_DMA_MEM_BUFFERABLE for M-class cpus >> ARM: dma-mapping: Remove traces of NOMMU code >> >> .../bindings/reserved-memory/reserved-memory.txt | 3 + >> arch/arm/Kconfig | 1 + >> arch/arm/include/asm/dma-mapping.h | 2 +- >> arch/arm/mm/Kconfig | 2 +- >> arch/arm/mm/Makefile | 5 +- >> arch/arm/mm/dma-mapping-nommu.c | 253 +++++++++++++++++++++ >> arch/arm/mm/dma-mapping.c | 29 +-- >> drivers/base/dma-coherent.c | 74 +++++- >> lib/dma-noop.c | 29 ++- >> 9 files changed, 354 insertions(+), 44 deletions(-) >> create mode 100644 arch/arm/mm/dma-mapping-nommu.c >> >