Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760626AbdCVP4O (ORCPT ); Wed, 22 Mar 2017 11:56:14 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36420 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760607AbdCVP4D (ORCPT ); Wed, 22 Mar 2017 11:56:03 -0400 From: Alexander Kochetkov To: Daniel Lezcano , Heiko Stuebner , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Thomas Gleixner , Mark Rutland , Rob Herring , Russell King , Caesar Wang , Huang Tao , Alexander Kochetkov Subject: [PATCH v7 6/7] ARM: dts: rockchip: add timer entries to rk3188 SoC Date: Wed, 22 Mar 2017 18:48:33 +0300 Message-Id: <1490197714-25415-7-git-send-email-al.kochet@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1490197714-25415-1-git-send-email-al.kochet@gmail.com> References: <1490197714-25415-1-git-send-email-al.kochet@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1473 Lines: 47 The patch add two timers to all rk3188 based boards. The first timer is from alive subsystem and it act as a backup for the local timers at sleep time. It act the same as other SoC rockchip timers already present in kernel. The second timer is from CPU subsystem and act as replacement for the arm-global-timer clocksource and sched clock. It run at stable frequency 24MHz. Signed-off-by: Alexander Kochetkov Reviewed-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b3e6a30..a20d501 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -106,6 +106,24 @@ }; }; + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; + clock-names = "timer", "pclk"; + clockevent; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + clocksource; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; -- 1.7.9.5