Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965352AbdCVRu5 (ORCPT ); Wed, 22 Mar 2017 13:50:57 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36537 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965311AbdCVRut (ORCPT ); Wed, 22 Mar 2017 13:50:49 -0400 From: Jagan Teki To: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matteo Lisi , Michael Trimarchi , Jagan Teki Subject: [PATCH 04/12] ARM: dts: imx6ul-isiot: Add i2c nodes Date: Wed, 22 Mar 2017 23:18:09 +0530 Message-Id: <1490204897-14525-5-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490204897-14525-1-git-send-email-jagan@openedev.com> References: <1490204897-14525-1-git-send-email-jagan@openedev.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1404 Lines: 61 From: Jagan Teki Add support for i2c nodes i2c1 and i2c2 on Is.IoT MX6UL eMMC variant boards. Cc: Shawn Guo Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/boot/dts/imx6ul-isiot.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index 5ccc3df..4697a04 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -71,6 +71,20 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &pwm8 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; @@ -95,6 +109,20 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + pinctrl_pwm8: pwm8grp { fsl,pins = < MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 -- 1.9.1