Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934898AbdCVRvs (ORCPT ); Wed, 22 Mar 2017 13:51:48 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:33743 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935722AbdCVRv2 (ORCPT ); Wed, 22 Mar 2017 13:51:28 -0400 From: Jagan Teki To: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matteo Lisi , Michael Trimarchi , Jagan Teki Subject: [PATCH 12/12] ARM: dts: imx6qdl-icore-rqs: Add CAN nodes Date: Wed, 22 Mar 2017 23:18:17 +0530 Message-Id: <1490204897-14525-13-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490204897-14525-1-git-send-email-jagan@openedev.com> References: <1490204897-14525-1-git-send-email-jagan@openedev.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2352 Lines: 96 From: Jagan Teki Add support for can1 and can2 nodes on Engicam i.CoreM6 RQS QDL module boards. Cc: Shawn Guo Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- arch/arm/boot/dts/imx6dl-icore-rqs.dts | 8 ++++++++ arch/arm/boot/dts/imx6q-icore-rqs.dts | 8 ++++++++ arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts index cf42c2f..f28577b 100644 --- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts +++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts @@ -49,3 +49,11 @@ model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; compatible = "engicam,imx6-icore-rqs", "fsl,imx6dl"; }; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts index e451b4c..21832f0 100644 --- a/arch/arm/boot/dts/imx6q-icore-rqs.dts +++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts @@ -62,6 +62,14 @@ }; }; +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + &i2c3 { codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index 5fab5be..4ccb08d 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -120,6 +120,18 @@ }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + &clks { assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; @@ -271,6 +283,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -- 1.9.1