Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933951AbdCWKnV (ORCPT ); Thu, 23 Mar 2017 06:43:21 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:33564 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751587AbdCWKnU (ORCPT ); Thu, 23 Mar 2017 06:43:20 -0400 Date: Thu, 23 Mar 2017 16:13:10 +0530 From: afzal mohammed To: Russell King - ARM Linux , Greg Ungerer Cc: Vladimir Murzin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: nommu: access ID_PFR1 only if CPUID scheme Message-ID: <20170323104310.GA6941@afzalpc> References: <20170317164034.4036-1-afzal.mohd.ma@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170317164034.4036-1-afzal.mohd.ma@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 964 Lines: 29 Hi, On Fri, Mar 17, 2017 at 10:10:34PM +0530, afzal mohammed wrote: > Greg upon trying to boot no-MMU Kernel on ARM926EJ reported boot > failure. He root caused it to ID_PFR1 access introduced by the > commit mentioned in the fixes tag below. > > All CP15 processors need not have processor feature registers, only > for architectures defined by CPUID scheme would have it. Hence check > for it before accessing processor feature register, ID_PFR1. > > Fixes: f8300a0b5de0 ("ARM: 8647/2: nommu: dynamic exception base address setting") > Reported-by: Greg Ungerer > Signed-off-by: afzal mohammed Greg, can i add your Tested-by ? Regards afzal > --- > > Hi Russell, > > It would be good to have the fix go in during -rc, as, > > 1. Culprit commit went in during the last merge window > 2. Though nothing supported in mainline is known to be broken, the > original change needs to be modified to be reliable