Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756590AbdCWUsN (ORCPT ); Thu, 23 Mar 2017 16:48:13 -0400 Received: from mga03.intel.com ([134.134.136.65]:17445 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753647AbdCWUsL (ORCPT ); Thu, 23 Mar 2017 16:48:11 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,211,1486454400"; d="scan'208";a="80393429" From: "Liang, Kan" To: Peter Zijlstra CC: "mingo@redhat.com" , "acme@kernel.org" , "linux-kernel@vger.kernel.org" , "tglx@linutronix.de" , "eranian@google.com" , "jolsa@kernel.org" , "ak@linux.intel.com" Subject: RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Thread-Topic: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Thread-Index: AQHSpARyOIb5UUisk0KlFjSvZGKZaKGiWswAgACHZ8A= Date: Thu, 23 Mar 2017 20:48:06 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536BE9A6@SHSMSX103.ccr.corp.intel.com> References: <1490293551-5552-1-git-send-email-kan.liang@intel.com> <1490293551-5552-2-git-send-email-kan.liang@intel.com> <20170323203138.li45llrzfxcaqieu@hirez.programming.kicks-ass.net> In-Reply-To: <20170323203138.li45llrzfxcaqieu@hirez.programming.kicks-ass.net> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjI2ZGFjMWUtMjBhNS00ZWVmLWI5ZGEtZWY0YjRhYTIzYTdmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Im1Tc2pKNmwrUHVKeUFhRnFPWGtObmVEN3M1WStHYkR6Q05zNHNpclc0czA9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v2NKmLh9026287 Content-Length: 932 Lines: 26 > On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.liang@intel.com wrote: > > From: Kan Liang > > > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all > performance > > counters will be effected. There is no way to do per-counter freeze on > > smi. So it should not use the per-event interface (e.g. ioctl or event > > attribute) to set FREEZE_WHILE_SMM bit. > > > > Adds sysfs entry /sys/device/cpu/freeze_on_smi to set > FREEZE_WHILE_SMM > > bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages > > while in SMM. > > Value has to be 0 or 1. It will be applied to all possible cpus. > > So is there ever a good reason to not set this? For me, I don't see any drawbacks to set it unconditionally. But I'm not sure if there is someone else who may want the counter running in SMI. If there is no objection, I will set the FREEZE_WHILE_SMM bit unconditionally in next version. Thanks, Kan