Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936780AbdCXQWB (ORCPT ); Fri, 24 Mar 2017 12:22:01 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35779 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936624AbdCXQVb (ORCPT ); Fri, 24 Mar 2017 12:21:31 -0400 From: Jagan Teki To: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sascha Hauer , Fabio Estevam , Matteo Lisi , Michael Trimarchi , Jagan Teki Subject: [PATCH v2 02/15] ARM: dts: imx6ul-isiot: Add backlight support for lcdif Date: Fri, 24 Mar 2017 21:48:37 +0530 Message-Id: <1490372330-5611-3-git-send-email-jagan@openedev.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490372330-5611-1-git-send-email-jagan@openedev.com> References: <1490372330-5611-1-git-send-email-jagan@openedev.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1604 Lines: 65 From: Jagan Teki This patch add support for lcdif backlight on Is.IoT MX6UL variant boards. Cc: Shawn Guo Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki --- Changes for v2: - none arch/arm/boot/dts/imx6ul-isiot.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index 0b43699..5ccc3df 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -52,6 +52,29 @@ chosen { stdout-path = &uart1; }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 100000>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <100>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; }; &uart1 { @@ -72,6 +95,12 @@ }; &iomuxc { + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 -- 1.9.1