Subject: Re: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid
 L3C counter overflow
To: Mark Rutland <mark.rutland@arm.com>
References: <1489127325-112821-1-git-send-email-anurup.m@huawei.com>
 <20170321171605.GB29116@leverpostej> <58D4C006.2010907@gmail.com>
 <20170324114325.GC22771@leverpostej>
Cc: will.deacon@arm.com, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com,
        zhangshaokun@hisilicon.com, tanxiaojun@huawei.com,
        xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com,
        gabriele.paoloni@huawei.com, shiju.jose@huawei.com,
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        shyju.pv@huawei.com
From: Anurup M <anurupvasu@gmail.com>
Message-ID: <58D8B234.3020004@gmail.com>
Date: Mon, 27 Mar 2017 12:03:24 +0530
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On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
>>> How do we ensure that we don't take the interrupt in the middle of a
>>> > >sequence of accesses to the HW?
>> >
>> >The L3 cache and MN PMU does not use the overflow IRQ and it does
>> >not occur here
>> >as the interrupt Mask register is by default masked in hardware.
> I was referring to the timer interrupt which backs the hrtimer.
>
> i.e. how do we guarantee that hisi_hrtimer_callback() is not called
> while we are in the middle of a RMW sequence? Are interrupts disabled
> for all of those seqeunces?

The HW access via djtag read and write are protected by spin_lock_irqsave.

Thanks,
Anurup

> Thanks,
> Mark.