Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752909AbdC0KG7 (ORCPT ); Mon, 27 Mar 2017 06:06:59 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:34750 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752594AbdC0KGl (ORCPT ); Mon, 27 Mar 2017 06:06:41 -0400 MIME-Version: 1.0 In-Reply-To: <20170320215250.wwhq6lzwe45jmwks@rob-hp-laptop> References: <1489417599-31308-1-git-send-email-cedric.madianga@gmail.com> <1489417599-31308-2-git-send-email-cedric.madianga@gmail.com> <20170320215250.wwhq6lzwe45jmwks@rob-hp-laptop> From: "M'boumba Cedric Madianga" Date: Mon, 27 Mar 2017 12:06:10 +0200 Message-ID: Subject: Re: [PATCH 1/2] dt-bindings: Document the STM32 MDMA bindings To: Rob Herring Cc: Vinod Koul , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5387 Lines: 140 Hi Rob, 2017-03-20 22:52 GMT+01:00 Rob Herring : > On Mon, Mar 13, 2017 at 04:06:38PM +0100, M'boumba Cedric Madianga wrote: >> This patch adds documentation of device tree bindings for the STM32 MDMA >> controller. >> >> Signed-off-by: M'boumba Cedric Madianga >> Reviewed-by: Ludovic BARRE >> --- >> .../devicetree/bindings/dma/stm32-mdma.txt | 94 ++++++++++++++++++++++ >> 1 file changed, 94 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/dma/stm32-mdma.txt >> >> diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt >> new file mode 100644 >> index 0000000..26a930c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt >> @@ -0,0 +1,94 @@ >> +* STMicroelectronics STM32 MDMA controller >> + >> +The STM32 MDMA is a general-purpose direct memory access controller capable of >> +supporting 64 independent DMA channels with 256 HW requests. >> + >> +Required properties: >> +- compatible: Should be "st,stm32-mdma" > > Should be more specific. The compatible string is not specific enough ? I don't see how to specific more. > >> +- reg: Should contain MDMA registers location and length. This should include >> + all of the per-channel registers. >> +- interrupts: Should contain the MDMA interrupt. >> +- clocks: Should contain the input clock of the DMA instance. >> +- resets: Reference to a reset controller asserting the DMA controller. >> +- #dma-cells : Must be <5>. See DMA client paragraph for more details. >> + >> +Optional properties: >> +- dma-channels: Number of DMA channels supported by the controller. >> +- dma-requests: Number of DMA request signals supported by the controller. >> +- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via >> + AHB bus. > > I don't understand what this is. The MDMA is able to address memories and devices from AHB bus or AXI bus. The MDMA has a little different way of working to address AHB device/memory and AXI device/memory. In STM32H7 platform, almost all devices are addressed by AXI bus. But we have some memories adress by AHB bus. So, we add these parameter to be able to handle this. > >> + >> +Example: > > Put the 2 examples together. OK > >> + >> + mdma1: dma@52000000 { >> + compatible = "st,stm32-mdma"; >> + reg = <0x52000000 0x1000>; >> + interrupts = <122>; >> + clocks = <&clk_dummy>; >> + resets = <&rcc 992>; >> + #dma-cells = <5>; >> + dma-channels = <16>; >> + dma-requests = <32>; >> + st,ahb-addr-masks = <0x20000000>, <0x00000000>; >> + }; >> + >> +* DMA client >> + >> +DMA clients connected to the STM32 MDMA controller must use the format >> +described in the dma.txt file, using a six-cell specifier for each channel: >> +a phandle to the MDMA controller plus the following five integer cells: >> + >> +1. The request line number >> +2. The priority level >> + 0x00: Low >> + 0x01: Medium >> + 0x10: High >> + 0x11: Very high >> +3. A 32bit mask specifying the DMA channel configuration >> + -bit 0-1: Source increment mode >> + 0x00: Source address pointer is fixed >> + 0x10: Source address pointer is incremented after each data transfer >> + 0x11: Source address pointer is decremented after each data transfer >> + -bit 2-3: Destination increment mode >> + 0x00: Destination address pointer is fixed >> + 0x10: Destination address pointer is incremented after each data >> + transfer >> + 0x11: Destination address pointer is decremented after each data >> + transfer >> + -bit 8-9: Source increment offset size >> + 0x00: byte (8bit) >> + 0x01: half-word (16bit) >> + 0x10: word (32bit) >> + 0x11: double-word (64bit) >> + -bit 10-11: Destination increment offset size >> + 0x00: byte (8bit) >> + 0x01: half-word (16bit) >> + 0x10: word (32bit) >> + 0x11: double-word (64bit) >> +-bit 25-18: The number of bytes to be transferred in a single transfer >> + (min = 1 byte, max = 128 bytes) >> +-bit 29:28: Trigger Mode >> + 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) >> + 0x01: Each MDMA request triggers a block transfer (max 64K bytes) >> + 0x10: Each MDMA request triggers a repeated block transfer >> + 0x11: Each MDMA request triggers a linked list transfer >> +4. A 32bit value specifying the register to be used to acknowledge the request >> + if no HW ack signal is used by the MDMA client >> +5. A 32bit mask specifying the value to be written to acknowledge the request >> + if no HW ack signal is used by the MDMA client >> + >> +Example: >> + >> + i2c4: i2c@5c002000 { >> + compatible = "st,stm32f7-i2c"; >> + reg = <0x5c002000 0x400>; >> + interrupts = , >> + ; >> + clocks = <&clk_hsi>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, >> + <&mdma1 37 0x0 0x40002 0x0 0x0>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> -- >> 1.9.1 >>