Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751904AbdC0RNE (ORCPT ); Mon, 27 Mar 2017 13:13:04 -0400 Received: from mga05.intel.com ([192.55.52.43]:37051 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751367AbdC0RNC (ORCPT ); Mon, 27 Mar 2017 13:13:02 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,232,1486454400"; d="scan'208";a="81127878" From: "Liang, Kan" To: Borislav Petkov CC: "peterz@infradead.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , "acme@kernel.org" , "eranian@google.com" , "jolsa@kernel.org" , "ak@linux.intel.com" Subject: RE: [PATCH V2 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions Thread-Topic: [PATCH V2 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions Thread-Index: AQHSpxOXdf0RmTi9aEmLRJpirD7KsqGoYhUAgACHrvA= Date: Mon, 27 Mar 2017 17:12:48 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536C5BFE@SHSMSX103.ccr.corp.intel.com> References: <1490629658-4308-1-git-send-email-kan.liang@intel.com> <1490629658-4308-2-git-send-email-kan.liang@intel.com> <20170327165710.zvqa7y7e6adby5bc@pd.tnic> In-Reply-To: <20170327165710.zvqa7y7e6adby5bc@pd.tnic> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjYxOTVjOTgtNWE3Mi00MTFlLWFiY2MtN2EyMzZmYWY2MjQ4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlwvQ3ZyNFp4Rmg5am9vSVF3MnhmSXhyVUk1Y2VwaHorRXNHZUxraEdEWTFNPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v2RHDE3o018170 Content-Length: 1805 Lines: 64 > > On Mon, Mar 27, 2017 at 08:47:37AM -0700, kan.liang@intel.com wrote: > > From: Kan Liang > > > > Having msr_set/clear_bit on many cpus or given CPU can avoid extra > > unnecessory IPIs > > How does that happen? > My previous patch did a read-modify-write operation. Compared with the single operation set/clear, it will has extra IPIs. Sorry for the confusing wording. I will change the description. > You have smp_call_function_many() sending IPIs to each CPU in the mask. > Doesn't look like avoiding anything to me. > > Now if you want to have interfaces set/clear_bit_on_cpu(s), that's a > different story. > > And those actually double the amount of IPIs the moment you do a read- > modify-write operation on the MSR, i.e., you want to read *and* write > afterwards. > > If you only want to do a single operation - set or clear - like you're doing in > your other patch, then I guess that's fine as it wraps the > smp_call_function* boilerplate code. > > > and simplify MSR content manipulation, when it only needs to flip a > > bit. > > There is already msr_set/clear_bit, but missing the _on_cpu and > > _on_cpus version. > > > > Signed-off-by: Kan Liang > > --- > > arch/x86/include/asm/msr.h | 29 ++++++++++++++++++ > > arch/x86/lib/msr-smp.c | 76 > ++++++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 105 insertions(+) > > > > diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h > > index 898dba2..9bc999b 100644 > > --- a/arch/x86/include/asm/msr.h > > +++ b/arch/x86/include/asm/msr.h > > @@ -20,6 +20,11 @@ struct msr { > > }; > > }; > > > > +struct msr_bit_info { > > + u32 msr_no; > > + u8 bit; > > +}; > > No, not *another* struct msr*info. Please reuse msr_info. > OK. Thanks, Kan