Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754815AbdC1IhC (ORCPT ); Tue, 28 Mar 2017 04:37:02 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:49518 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754643AbdC1IhB (ORCPT ); Tue, 28 Mar 2017 04:37:01 -0400 Date: Tue, 28 Mar 2017 10:36:48 +0200 (CEST) From: Thomas Gleixner To: Kan Liang cc: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org, bp@alien8.de, acme@kernel.org, eranian@google.com, jolsa@kernel.org, ak@linux.intel.com Subject: Re: [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions In-Reply-To: <1490639448-4147-2-git-send-email-kan.liang@intel.com> Message-ID: References: <1490639448-4147-1-git-send-email-kan.liang@intel.com> <1490639448-4147-2-git-send-email-kan.liang@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1318 Lines: 47 On Mon, 27 Mar 2017, kan.liang@intel.com wrote: > From: Kan Liang > > To flip a MSR bit on many CPUs or specific CPU, currently it has to do > read-modify-write operation on the MSR through rd/wrmsr_on_cpu(s). > It actually sends two IPIs to the given CPU. The IPIs are the least of the problems, really. The real problem is that rdmsr_on_cpu() wrmsr_on_cpu() is not atomic. That's what wants to be solved. The reduction of IPIs just a side effect. > #else /* CONFIG_SMP */ > +static inline int msr_set_bit_on_cpu(unsigned int cpu, u32 msr, u8 bit) > +{ > + return msr_set_bit(msr, bit); > +} > + > +static inline int msr_clear_bit_on_cpu(unsigned int cpu, u32 msr, u8 bit) > +{ > + return msr_clear_bit(msr, bit); > +} > + > +static inline void msr_set_bit_on_cpus(const struct cpumask *mask, u32 msr, u8 bit) > +{ > + msr_set_bit(msr, bit); > +} > + > +static inline void msr_clear_bit_on_cpus(const struct cpumask *mask, u32 msr, u8 bit) > +{ > + msr_clear_bit(msr, bit); > +} This is utter crap because it's fundamentaly different from the SMP version. msr_set/clear_bit() are not protected by anyhting. And in your call site this is invoked from fully preemptible context. What protects against context switch and interrupts fiddling with DEBUGMSR? Thanks, tglx