Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754825AbdC1Im1 (ORCPT ); Tue, 28 Mar 2017 04:42:27 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:49568 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754644AbdC1Im0 (ORCPT ); Tue, 28 Mar 2017 04:42:26 -0400 Date: Tue, 28 Mar 2017 10:42:13 +0200 (CEST) From: Thomas Gleixner To: Kan Liang cc: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org, bp@alien8.de, acme@kernel.org, eranian@google.com, jolsa@kernel.org, ak@linux.intel.com Subject: Re: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI In-Reply-To: <1490639448-4147-3-git-send-email-kan.liang@intel.com> Message-ID: References: <1490639448-4147-1-git-send-email-kan.liang@intel.com> <1490639448-4147-3-git-send-email-kan.liang@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 789 Lines: 28 On Mon, 27 Mar 2017, kan.liang@intel.com wrote: > + > + if (val) > + msr_set_bit_on_cpus(cpu_possible_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); > + else > + msr_clear_bit_on_cpus(cpu_possible_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); This is still not protected against CPU hotplug. What's so hard about: get_online_cpus(); if (val) { msr_set_bit_on_cpus(cpu_online_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); } else { msr_clear_bit_on_cpus(cpu_online_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); } put_online_cpus(); Aside of that, when this is set to SMI freeze, what causes a CPU which comes online after that point to set the bit as well? Nothing AFAICT. Thanks, tglx