Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932458AbdC1NX1 (ORCPT ); Tue, 28 Mar 2017 09:23:27 -0400 Received: from mga14.intel.com ([192.55.52.115]:6351 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932118AbdC1NXX (ORCPT ); Tue, 28 Mar 2017 09:23:23 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,236,1486454400"; d="scan'208";a="1112935130" From: "Liang, Kan" To: Thomas Gleixner CC: "peterz@infradead.org" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" , "acme@kernel.org" , "eranian@google.com" , "jolsa@kernel.org" , "ak@linux.intel.com" Subject: RE: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI Thread-Topic: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI Thread-Index: AQHSpypsqeNowSNArUWHclRT7fZ2XKGpafOAgADSz0A= Date: Tue, 28 Mar 2017 13:23:00 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536C61D3@SHSMSX103.ccr.corp.intel.com> References: <1490639448-4147-1-git-send-email-kan.liang@intel.com> <1490639448-4147-3-git-send-email-kan.liang@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWQ0ZTc5YjctMzYwOC00MDIwLWJiYWUtYWIyNzJmNWFiNzYxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImhxRGhoZkNaK3VZcEVPZ3VoSVpjZzkyS1BzT2RnZ3ZcL1J1bDhmMU1reE9rPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v2SDjlVW030546 Content-Length: 1290 Lines: 52 > > On Mon, 27 Mar 2017, kan.liang@intel.com wrote: > > + > > + if (val) > > + msr_set_bit_on_cpus(cpu_possible_mask, > MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); > > + else > > + msr_clear_bit_on_cpus(cpu_possible_mask, > MSR_IA32_DEBUGCTLMSR, > > +DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); > > This is still not protected against CPU hotplug. What's so hard about: > > get_online_cpus(); > > if (val) { > msr_set_bit_on_cpus(cpu_online_mask, > MSR_IA32_DEBUGCTLMSR, > DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); > } else { > msr_clear_bit_on_cpus(cpu_online_mask, > MSR_IA32_DEBUGCTLMSR, > > DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); > } > > put_online_cpus(); > > Aside of that, when this is set to SMI freeze, what causes a CPU which > comes online after that point to set the bit as well? Nothing AFAICT. > > I've patched the intel_pmu_cpu_starting. I think it guarantees that the new online CPU is set. @@ -3174,6 +3174,11 @@ static void intel_pmu_cpu_starting(int cpu) cpuc->lbr_sel = NULL; + if (x86_pmu.attr_freeze_on_smi) + msr_set_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); + else + msr_clear_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT); + if (!cpuc->shared_regs) return; Thanks, Kan