Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755755AbdC1Na6 (ORCPT ); Tue, 28 Mar 2017 09:30:58 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:60096 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754909AbdC1Mkg (ORCPT ); Tue, 28 Mar 2017 08:40:36 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Bob Ham , Chen-Yu Tsai , Maxime Ripard Subject: [PATCH 4.10 077/111] clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock Date: Tue, 28 Mar 2017 14:31:03 +0200 Message-Id: <20170328122918.883831197@linuxfoundation.org> X-Mailer: git-send-email 2.12.1 In-Reply-To: <20170328122915.640228468@linuxfoundation.org> References: <20170328122915.640228468@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1128 Lines: 33 4.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Chen-Yu Tsai commit 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d upstream. The enable bit offset for the hdmi-ddc module clock is wrong. It is pointing to the main hdmi module clock enable bit. Reported-by: Bob Ham Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Greg Kroah-Hartman --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_cl 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); -static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0); +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0); static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);