Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755450AbdC1Ri7 (ORCPT ); Tue, 28 Mar 2017 13:38:59 -0400 Received: from mga09.intel.com ([134.134.136.24]:7187 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753150AbdC1Ri5 (ORCPT ); Tue, 28 Mar 2017 13:38:57 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,237,1486454400"; d="scan'208";a="80281211" From: "Liang, Kan" To: Thomas Gleixner CC: "peterz@infradead.org" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" , "acme@kernel.org" , "eranian@google.com" , "jolsa@kernel.org" , "ak@linux.intel.com" Subject: RE: [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions Thread-Topic: [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions Thread-Index: AQHSpypsnxJm4DPR6EK9CjNZFKPIwqGpaG8AgACTEICAAIf3IA== Date: Tue, 28 Mar 2017 17:38:13 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536C63BB@SHSMSX103.ccr.corp.intel.com> References: <1490639448-4147-1-git-send-email-kan.liang@intel.com> <1490639448-4147-2-git-send-email-kan.liang@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODlmMzI0ZjEtMzVhYy00MTRhLWE3OGItOGQ4MmFmMzI5MGFiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IldIbnFxb0xpY0U1eGVLREMrRjZTVVwvNjFzbVBEXC9FUGNEV2VKK25qT3MxZz0ifQ== x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v2SHe4Nx000330 Content-Length: 1940 Lines: 78 . > > msr_set/clear_bit() are not protected by anyhting. And in your call > > site this is invoked from fully preemptible context. What protects > > against context switch and interrupts fiddling with DEBUGMSR? > > And thinking more about that whole interface. It's just overkill. > > diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c index > d1dee753b949..35763927adaa 100644 > --- a/arch/x86/lib/msr.c > +++ b/arch/x86/lib/msr.c > @@ -58,7 +58,7 @@ int msr_write(u32 msr, struct msr *m) > return wrmsrl_safe(msr, m->q); > } > > -static inline int __flip_bit(u32 msr, u8 bit, bool set) > +int msr_flip_bit(u32 msr, u8 bit, bool set) > { > struct msr m, m1; > int err = -EINVAL; > @@ -85,6 +85,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set) > > return 1; > } > +EXPORT_SYMBOL_GPL(msr_flip_bit); > > /** > * Set @bit in a MSR @msr. > @@ -96,7 +97,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set) > */ > int msr_set_bit(u32 msr, u8 bit) > { > - return __flip_bit(msr, bit, true); > + return msr_flip_bit(msr, bit, true); > } > > /** > @@ -109,7 +110,7 @@ int msr_set_bit(u32 msr, u8 bit) > */ > int msr_clear_bit(u32 msr, u8 bit) > { > - return __flip_bit(msr, bit, false); > + return msr_flip_bit(msr, bit, false); > } > > #ifdef CONFIG_TRACEPOINTS > > And in the driver: > > static void flip_smm_bit(void *data) > { > int val = *(int *)data; > > msr_flip_bit(DEBUGMSR, SMMBIT, val); > } > > And in the write function: > > smp_call_function(flip_smm_bit, &val, 1); > > That avoids all the extra interfaces and requires less code and less text foot > print when unused ..... > Thanks. It simplify the code very much. I think we still need to protect the smp_call_function in the driver, right? Would be the following code enough? get_online_cpus(); preempt_disable(); smp_call_function(flip_smm_bit, &val, 1); preempt_enable(); put_online_cpus(); Thanks, Kan