Date: Wed, 29 Mar 2017 18:27:40 +0800
From: Leo Yan <leo.yan@linaro.org>
To: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Cc: Jonathan Corbet <corbet@lwn.net>, Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>, Wei Xu <xuwei5@hisilicon.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will.deacon@arm.com>, Andy Gross <andy.gross@linaro.org>,
        David Brown <david.brown@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Guodong Xu <guodong.xu@linaro.org>,
        John Stultz <john.stultz@linaro.org>, linux-doc@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org,
        linux-soc@vger.kernel.org, linux-clk@vger.kernel.org,
        mike.leach@linaro.org, sudeep.holla@arm.com
Subject: Re: [PATCH v5 6/9] coresight: add support for CPU debug module
Message-ID: <20170329102740.GA20804@leoy-linaro>
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On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:

[...]

> >>>+	if (mode == EDDEVID_IMPL_NONE) {
> >>>+		drvdata->edpcsr_present  = false;
> >>>+		drvdata->edcidsr_present = false;
> >>>+		drvdata->edvidsr_present = false;
> >>>+	} else if (mode == EDDEVID_IMPL_EDPCSR) {
> >>>+		drvdata->edpcsr_present  = true;
> >>>+		drvdata->edcidsr_present = false;
> >>>+		drvdata->edvidsr_present = false;
> >>>+	} else if (mode == EDDEVID_IMPL_EDPCSR_EDCIDSR) {
> >>>+		if (!IS_ENABLED(CONFIG_64BIT) &&
> >>>+			(pcsr_offset == EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32))
> >>>+			drvdata->edpcsr_present = false;
> >>>+		else
> >>>+			drvdata->edpcsr_present = true;
> >>
> >>Sorry, I forgot why we do this check only in this mode. Shouldn't this be
> >>common to all modes (of course which implies PCSR is present) ?
> >
> >No. PCSROffset is defined differently in ARMv7 and ARMv8; So finally we
> >simplize PCSROffset value :
> >0000 - Sample offset applies based on the instruction state (indicated by PCSR[0])
> >0001 - No offset applies.
> >0010 - No offset applies, but do not use in AArch32 mode!
> >
> >So we need handle the corner case is when CPU runs AArch32 mode and
> >PCSRoffset = 'b0010. Other cases the pcsr should be present.
> 
> I understand that reasoning. But my question is, why do we check for PCSROffset
> only when mode == EDDEVID_IMPL_EDPCSR_EDCIDSR and not for say mode == EDDEVID_IMPL_EDPCSR or
> any other mode where PCSR is present.

Sorry I misunderstood your question.

I made mistake when I analyzed the possbile combination for mode and
PCSROffset so I thought it's the only case should handle:
{ EDDEVID_IMPL_EDPCSR_EDCIDSR, EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 }

Below three combinations are possible to exist; so you are right, I
should move this out for the checking:
{ EDDEVID_IMPL_NONE,           EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 }
{ EDDEVID_IMPL_EDPCSR_EDCIDSR, EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 }
{ EDDEVID_IMPL_FULL,           EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 }

Thanks,
Leo Yan