Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756054AbdC2Lnc (ORCPT ); Wed, 29 Mar 2017 07:43:32 -0400 Received: from bastet.se.axis.com ([195.60.68.11]:56120 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756001AbdC2LmX (ORCPT ); Wed, 29 Mar 2017 07:42:23 -0400 Subject: Re: [GIT PULL] PCI: Support for configurable PCI endpoint To: Kishon Vijay Abraham I , Bjorn Helgaas , Joao Pinto , , , , , , References: <20170327094520.3129-1-kishon@ti.com> CC: , From: Niklas Cassel Message-ID: <0cfe5acf-332c-00c9-e5d5-1403c4e80ebe@axis.com> Date: Wed, 29 Mar 2017 13:42:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.6.0 MIME-Version: 1.0 In-Reply-To: <20170327094520.3129-1-kishon@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.0.5.60] X-ClientProxiedBy: XBOX02.axis.com (10.0.5.16) To XBOX02.axis.com (10.0.5.16) X-TM-AS-GCONF: 00 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3104 Lines: 77 On 03/27/2017 11:44 AM, Kishon Vijay Abraham I wrote: > Hi Bjorn, > > Please find the pull request for PCI endpoint support below. I've > also included all the history here. > > Changes from v4: > *) add #syscon-cells property and used of_parse_phandle_with_args > to perform a configuration in syscon module (as suggested by > Rob Herring) > *) Remove unnecessary white space. > > Changes from v3: > *) fixed a typo and adapted to https://lkml.org/lkml/2017/3/13/562. > > Changes from v2: > *) changed the configfs structure as suggested by Christoph Hellwig. With > this change the framework creates configfs entry for EP function driver > and EP controller. Previously these entries have to be created by the > the user. (Haven't changed the epc core or epf core except for invoking > configfs APIs to create entries for EP function driver and EP controller. > That's mostly because the EP function device can still be created by > directly invoking the epf core API without using configfs). > *) Now the user has to use configfs entry 'start' to start the link. > This was previously done by the function driver. However in the case of > multi function EP, the function driver shouldn't start the link. > > Changes from v1: > *) The preparation patches for adding EP support is removed and is sent > separately > *) Added device ID for DRA74x/DRA72x and used it instead of > using "PCI_ANY_ID" > *) Added userguide for PCI endpoint test function > > Major Improvements from RFC: > *) support multi-function devices (hw supported not virtual) > *) Access host side buffers > *) Raise MSI interrupts > *) Add user space program to use the host side PCI driver > *) Adapt all other users of designware to use the new design (only > compile tested. Since I have only dra7xx boards, the new design > has only been tested in dra7xx. I'd require the help of others > to test the platforms they have access to). > > This series has been developed over 4.11-rc1 + [1] > [1] -> https://lkml.org/lkml/2017/3/13/562 > > Let me know if this has to be re-based to some of your branch. > > Thanks > Kishon > > The following changes since commit 623e87fec8ab7867fb51b3079196bd10718a60ce: > > PCI: dwc: dra7xx: Push request_irq call to the bottom of probe (2017-03-22 20:35:30 +0530) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git tags/pci-endpoint-for-4.12 > > for you to fetch changes up to e98bf80074be4654faae42fe0f5a622a776b6fdd: > > ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP (2017-03-27 15:08:22 +0530) > > ---------------------------------------------------------------- FWIW: I've tested Kishon's tag pci-endpoint-for-4.12 and PCIe on artpec6 SoC is still working fine. I also included the DRA7xx PCIe driver in my kernel so that pcie-designware-ep.c gets built. My only worry is that the code in pcie-designware-ep.c is not compile tested if DRA7xx is not selected (as it is the only driver using PCIE_DW_EP at the moment).