Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932785AbdC2Tuc (ORCPT ); Wed, 29 Mar 2017 15:50:32 -0400 Received: from hermes.aosc.io ([172.82.152.187]:45446 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753325AbdC2Tt1 (ORCPT ); Wed, 29 Mar 2017 15:49:27 -0400 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH v3 09/11] ARM: dts: sun8i: add DE2 nodes for V3s SoC Date: Thu, 30 Mar 2017 03:46:11 +0800 Message-Id: <20170329194613.55548-10-icenowy@aosc.io> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170329194613.55548-1-icenowy@aosc.io> References: <20170329194613.55548-1-icenowy@aosc.io> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3146 Lines: 129 From: Icenowy Zheng Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON which have RGB LCD output. Add device nodes for it as well as the TCON. Signed-off-by: Icenowy Zheng --- Changes in v3: - Change the size of de2_clocks regs according to the binding example. arch/arm/boot/dts/sun8i-v3s.dtsi | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 71075969e5e6..ae23746731a8 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -41,6 +41,10 @@ */ #include +#include +#include +#include +#include / { #address-cells = <1>; @@ -59,6 +63,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&de2_mixer0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -93,6 +103,83 @@ #size-cells = <1>; ranges; + de2_clocks: clock@01000000 { + compatible = "allwinner,sun50i-h5-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + de2_mixer0: mixer@01100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&de2_clocks CLK_MIXER0>, + <&de2_clocks CLK_BUS_MIXER0>; + clock-names = "mod", + "bus"; + resets = <&de2_clocks RST_MIXER0>; + assigned-clocks = <&de2_clocks CLK_MIXER0>; + assigned-clock-rates = <150000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; -- 2.12.0