Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933043AbdC3J7Q (ORCPT ); Thu, 30 Mar 2017 05:59:16 -0400 Received: from mga03.intel.com ([134.134.136.65]:16991 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932977AbdC3J7N (ORCPT ); Thu, 30 Mar 2017 05:59:13 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,246,1486454400"; d="scan'208";a="949740169" Message-ID: <1490867763.708.62.camel@linux.intel.com> Subject: Re: [PATCH] serial: Do not treat the IIR register as a bitfield From: Andy Shevchenko To: Olliver Schinagl , Greg Kroah-Hartman , Jiri Slaby , Laxman Dewangan , Stephen Warren , Thierry Reding , Alexandre Courbot , "David S . Miller" Cc: dev@linux-sunxi.org, Ed Blake , Alexander Sverdlin , Yegor Yefremov , Wan Ahmad Zainie , Kefeng Wang , Heikki Krogerus , Heiko Stuebner , Jason Uy , Douglas Anderson , Peter Hurley , Tony Lindgren , Vignesh R , Thor Thayer , David Lechner , Jan Kiszka , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, sparclinux@vger.kernel.org Date: Thu, 30 Mar 2017 12:56:03 +0300 In-Reply-To: <20170329184431.6226-1-oliver@schinagl.nl> References: <20170329184431.6226-1-oliver@schinagl.nl> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1078 Lines: 31 On Wed, 2017-03-29 at 20:44 +0200, Olliver Schinagl wrote: > It seems that at some point, someone made the assumption that the UART > Interrupt ID Register was a bitfield and started to check if certain > bits where set. > > Actually however the register contains interrupt ID's where only the > MSB > seems to be used singular and the rest share at least one bit. Thus > doing bitfield operations is wrong. > > This patch cleans up the serial_reg include file by ordering it and > replacing the UART_IIR_ID 'mask' with a proper mask for the register. > The OMAP uart appears to have used the two commonly 'reserved' bits 4 > and 5 and thus get an UART_IIR_EXT_MASK for these two bits. > > This patch then goes over all UART_IIR_* users and changes the code > from > bitfield checking, to ID checking instead. Looking to implementation I would rather go with some helper like int serial_in_IIR(port, [additional mask]) { return port->serial_in(port, UART_IIR) & (_IIR_MASK [| additional mask]); } -- Andy Shevchenko Intel Finland Oy