Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933310AbdC3KAf (ORCPT ); Thu, 30 Mar 2017 06:00:35 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35208 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932395AbdC3KAb (ORCPT ); Thu, 30 Mar 2017 06:00:31 -0400 Subject: Re: [PATCH V1 1/1] mtd: mtk-nor: set controller to 4B mode with large capacity flash To: Guochun Mao , Boris Brezillon References: <1490862222-723-1-git-send-email-guochun.mao@mediatek.com> <1490862222-723-2-git-send-email-guochun.mao@mediatek.com> Cc: David Woodhouse , Richard Weinberger , Cyrille Pitchen , Rob Herring , Mark Rutland , Matthias Brugger , Russell King , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org From: Marek Vasut Message-ID: <9d3a292b-8298-81ec-a049-b021616f1ddf@gmail.com> Date: Thu, 30 Mar 2017 12:00:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.4.0 MIME-Version: 1.0 In-Reply-To: <1490862222-723-2-git-send-email-guochun.mao@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1312 Lines: 38 On 03/30/2017 10:23 AM, Guochun Mao wrote: > when nor's size larger than 16MByte, nor and controller should > enter 4Byte mode simultaneously. > > Signed-off-by: Guochun Mao > --- > drivers/mtd/spi-nor/mtk-quadspi.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c > index e661877..05cd8a8 100644 > --- a/drivers/mtd/spi-nor/mtk-quadspi.c > +++ b/drivers/mtd/spi-nor/mtk-quadspi.c > @@ -369,6 +369,13 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, > /* We only handle 1 byte */ > ret = mt8173_nor_wr_sr(mt8173_nor, *buf); > break; > + case SPINOR_OP_EN4B: > + /* Set nor controller to 4-byte address mode, > + * and simultaneously set nor flash. > + * This case should cooperate with default operation. > + */ > + writeb(readb(mt8173_nor->base + MTK_NOR_DUAL_REG) | 0x10, > + mt8173_nor->base + MTK_NOR_DUAL_REG); And what happens on READ then ? Who clears that bit when protocol changes ? You probably want something like cqspi_set_protocol() instead, which is invoked from {read,write}{,_reg}() and erase(). > default: > ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); > if (ret) > -- Best regards, Marek Vasut