Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934000AbdC3Nb6 (ORCPT ); Thu, 30 Mar 2017 09:31:58 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:40509 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933387AbdC3Nb4 (ORCPT ); Thu, 30 Mar 2017 09:31:56 -0400 Date: Thu, 30 Mar 2017 15:31:36 +0200 From: Andrew Lunn To: Vivien Didelot Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@savoirfairelinux.com, "David S. Miller" , Florian Fainelli Subject: Re: [PATCH net-next 1/9] net: dsa: mv88e6xxx: move PVT description in info Message-ID: <20170330133136.GA17879@lunn.ch> References: <20170329203020.27042-1-vivien.didelot@savoirfairelinux.com> <20170329203020.27042-2-vivien.didelot@savoirfairelinux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170329203020.27042-2-vivien.didelot@savoirfairelinux.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 560 Lines: 14 On Wed, Mar 29, 2017 at 04:30:12PM -0400, Vivien Didelot wrote: > Not all Marvell switch chips feature a Cross-chip Port VLAN Table (PVT). > > Chips with a PVT use the same implementation, so a new mv88e6xxx_ops > member won't be necessary yet. Add a "pvt" boolean member to the > mv88e6xxx_info structure and kill the obsolete MV88E6XXX_FLAGS_PVT flag. > > Add a mv88e6xxx_has_pvt helper to wrap future checks of that condition. > > Signed-off-by: Vivien Didelot Reviewed-by: Andrew Lunn Andrew