Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933897AbdC3Ne1 (ORCPT ); Thu, 30 Mar 2017 09:34:27 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:40514 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933217AbdC3NeZ (ORCPT ); Thu, 30 Mar 2017 09:34:25 -0400 Date: Thu, 30 Mar 2017 15:34:23 +0200 From: Andrew Lunn To: Vivien Didelot Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@savoirfairelinux.com, "David S. Miller" , Florian Fainelli Subject: Re: [PATCH net-next 2/9] net: dsa: mv88e6xxx: use 4-bit port for PVT data Message-ID: <20170330133423.GB17879@lunn.ch> References: <20170329203020.27042-1-vivien.didelot@savoirfairelinux.com> <20170329203020.27042-3-vivien.didelot@savoirfairelinux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170329203020.27042-3-vivien.didelot@savoirfairelinux.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 833 Lines: 18 On Wed, Mar 29, 2017 at 04:30:13PM -0400, Vivien Didelot wrote: > The Cross-chip Port Based VLAN Table (PVT) supports two indexing modes, > one using 5-bit for device and 4-bit for port, the other using 4-bit for > device and 5-bit for port, configured via the Global 2 Misc register. > > Only 4 bits for the source port are needed when interconnecting 88E6xxx > switch devices since they all support less than 16 physical ports. The > full 5 bits are needed when interconnecting a device with 98DXxxx switch > devices since they support more than 16 physical ports. > > Add a mv88e6xxx_pvt_setup helper to set the 4-bit port PVT mode, which > will be extended later to also initialize the PVT content. > > Signed-off-by: Vivien Didelot Reviewed-by: Andrew Lunn Andrew