Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934772AbdC3TqS convert rfc822-to-8bit (ORCPT ); Thu, 30 Mar 2017 15:46:18 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14253 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933661AbdC3TqP (ORCPT ); Thu, 30 Mar 2017 15:46:15 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 30 Mar 2017 12:46:14 -0700 From: Aniruddha Banerjee To: "tglx@linutronix.de" , Jonathan Hunter CC: "linux-kernel@vger.kernel.org" , "Thierry Reding" , Stephen Warren Subject: [PATCH 1/1] irq: add IRQF_TRIGGER_MASK on PPI by default Thread-Topic: [PATCH 1/1] irq: add IRQF_TRIGGER_MASK on PPI by default Thread-Index: AdKpjfIkScc3M0YyT7WT0x1AbRUc8A== Date: Thu, 30 Mar 2017 19:46:08 +0000 Message-ID: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.25.75.225] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 779 Lines: 24 add IRQF_TRIGGER_MASK on PPI by default so that the PPIs are not configured as edge-triggered, which may be wrong for certain GIC implementations such as the GIC-400 Signed-off-by: Aniruddha Banerjee --- kernel/irq/manage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 6b669593e7eb..9b2983cf9fd3 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1982,7 +1982,7 @@ int request_percpu_irq(unsigned int irq, irq_handler_t handler, return -ENOMEM; action->handler = handler; - action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; + action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_TRIGGER_MASK; action->name = devname; action->percpu_dev_id = dev_id; -- 2.11.0