Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932973AbdCaKHY convert rfc822-to-8bit (ORCPT ); Fri, 31 Mar 2017 06:07:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13264 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932342AbdCaKHW (ORCPT ); Fri, 31 Mar 2017 06:07:22 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 31 Mar 2017 03:04:00 -0700 From: Shardar Mohammed To: Laxman Dewangan , Olliver Schinagl , Greg Kroah-Hartman , "Jiri Slaby" , Stephen Warren , "Thierry Reding" , Alexandre Courbot CC: "linux-serial@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] serial: tegra: Map the iir register to default defines Thread-Topic: [PATCH] serial: tegra: Map the iir register to default defines Thread-Index: AQHSqUFsoB73X/6LZU+DGr0lGyKvNKGuuJrg Date: Fri, 31 Mar 2017 10:07:15 +0000 Message-ID: <83c51151685d4be7926f7f3982c59db8@bgmail102.nvidia.com> References: <20170329184806.6577-1-oliver@schinagl.nl> <58DCDB54.5040005@nvidia.com> In-Reply-To: <58DCDB54.5040005@nvidia.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.19.65.62] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1297 Lines: 29 Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK; Thanks, Shardar -----Original Message----- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl ; Greg Kroah-Hartman ; Jiri Slaby ; Stephen Warren ; Thierry Reding ; Alexandre Courbot Cc: linux-serial@vger.kernel.org; linux-tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End > of Data interrupt. > > Signed-off-by: Olliver Schinagl > --- Adding Shardar for verifications. Acked-by: Laxman Dewangan