Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933015AbdCaMHP convert rfc822-to-8bit (ORCPT ); Fri, 31 Mar 2017 08:07:15 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7694 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932732AbdCaMHO (ORCPT ); Fri, 31 Mar 2017 08:07:14 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 31 Mar 2017 05:07:12 -0700 From: Aniruddha Banerjee To: Marc Zyngier , Thomas Gleixner CC: Jonathan Hunter , "linux-kernel@vger.kernel.org" , Thierry Reding , "Stephen Warren" Subject: RE: [PATCH 1/1] irq: add IRQF_TRIGGER_MASK on PPI by default Thread-Topic: [PATCH 1/1] irq: add IRQF_TRIGGER_MASK on PPI by default Thread-Index: AdKpjfIkScc3M0YyT7WT0x1AbRUc8AAZwkgAAACExYAAB6x6IA== Date: Fri, 31 Mar 2017 12:07:06 +0000 Message-ID: <0eae4270857e4452ba76adca7f402360@bgmail102.nvidia.com> References: <6bb214e5-7007-8541-ca95-838542f95b2a@arm.com> In-Reply-To: <6bb214e5-7007-8541-ca95-838542f95b2a@arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.24.52.225] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1521 Lines: 35 > On 31/03/17 , Marc Zyngier wrote: > On 31/03/17 09:01, Thomas Gleixner wrote: > > On Thu, 30 Mar 2017, Aniruddha Banerjee wrote: > > > >> add IRQF_TRIGGER_MASK on PPI by default so that the PPIs are not > >> configured as edge-triggered, which may be wrong for certain GIC > >> implementations such as the GIC-400 > > > > The above is just useless blurb. > > > > I can't figure out at all WHY a generic interface has anything to do > > with edge trigger configuration. > > > > I assume this is (Nvidia) GIC specific nonsense, so why are you > > inflicting this on every caller of this interface unconditionally w/o > > explaining what the impact of this change might be and why it does not > > cause havoc for any existing caller? > > > > This is function is implemented in kernel/irq/ not in foo/gic/ so you > > better come up with some coherent explanation. > > Indeed. I'm not aware of anything wrong so far with GIC400, so this is most likely > referring to an integration issue. > > Furthermore, PPI triggers are usually not configurable on GIC400. My bet is that this is > only a DT issue, but in the absence of any coherent justification, it is hard to make an > educated guess... That was an awesome guess and we were in fact doing something very wrong in the DT. In the GIC-400 implementation, the PPI triggers are read-only. I was trying to configure the PPI as edge-triggered, and the writes were dropped in the process. A big thank you to Jon Hunter and Marc for pointing this out. Regards, Aniruddha.