Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751796AbdDCBvo (ORCPT ); Sun, 2 Apr 2017 21:51:44 -0400 Received: from mail-yw0-f196.google.com ([209.85.161.196]:32888 "EHLO mail-yw0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751033AbdDCBvm (ORCPT ); Sun, 2 Apr 2017 21:51:42 -0400 MIME-Version: 1.0 In-Reply-To: References: <20170331133728.GA23725@rajaneesh-OptiPlex-9010> From: Sathyanarayanan Kuppuswamy Natarajan Date: Sun, 2 Apr 2017 18:51:40 -0700 Message-ID: Subject: Re: [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset To: Andy Shevchenko Cc: Kuppuswamy Sathyanarayanan , Andy Shevchenko , Zha Qipeng , "dvhart@infradead.org" , Guenter Roeck , Wim Van Sebroeck , David Box , Rajneesh Bhardwaj , Platform Driver , "linux-kernel@vger.kernel.org" , linux-watchdog@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1658 Lines: 54 Yes, just applying this patch will fix the existing offset issue. On Sun, Apr 2, 2017 at 7:11 AM, Andy Shevchenko wrote: > On Sat, Apr 1, 2017 at 2:27 AM, Kuppuswamy Sathyanarayanan > wrote: >> According to Broxton APL PMC spec, gcr mem region starts >> at offset 0x1000 from ipc mem base address. In this driver, >> PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR >> memory region from IPC mem region. So we should use 0x1000(4K) >> as GCR offset. But currently this driver uses 0x1008 as GCT >> offset.This patch fixes this issue. > > > So, if I apply this one independently, would it fix an existin issue? > >> >> Signed-off-by: Kuppuswamy Sathyanarayanan >> --- >> drivers/platform/x86/intel_pmc_ipc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> Changes since v3: >> * Updated the commit history >> >> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c >> index 0651d47..0a33592 100644 >> --- a/drivers/platform/x86/intel_pmc_ipc.c >> +++ b/drivers/platform/x86/intel_pmc_ipc.c >> @@ -82,7 +82,7 @@ >> /* exported resources from IFWI */ >> #define PLAT_RESOURCE_IPC_INDEX 0 >> #define PLAT_RESOURCE_IPC_SIZE 0x1000 >> -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 >> +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 >> #define PLAT_RESOURCE_GCR_SIZE 0x1000 >> #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 >> #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 >> -- >> 2.7.4 >> > > > > -- > With Best Regards, > Andy Shevchenko -- -- Sathya