Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753111AbdDCNeO (ORCPT ); Mon, 3 Apr 2017 09:34:14 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:37276 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751515AbdDCNeN (ORCPT ); Mon, 3 Apr 2017 09:34:13 -0400 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.wolfsonmicro.com Date: Mon, 3 Apr 2017 14:34:34 +0100 From: Charles Keepax To: Daniel Baluta CC: Zidan Wang , Mark Brown , Zidan Wang , Liam Girdwood , Jaroslav Kysela , , Lars-Peter Clausen , , , Linux Kernel Mailing List , , , Subject: Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver configure its bit clock and frame clock Message-ID: <20170403133434.GU6986@localhost.localdomain> References: <1420615905-4078-1-git-send-email-zidan.wang@freescale.com> <1420615905-4078-2-git-send-email-zidan.wang@freescale.com> <20150114192703.GH3043@sirena.org.uk> <20150115133439.GA29323@b50113> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704030122 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1705 Lines: 50 On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote: > On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote: > > On Wed, Jan 14, 2015 at 07:27:03PM +0000, Mark Brown wrote: > >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote: > > I found it can't generate bclk for S20_3LE data format. > > > > For 2 channel S20_3LE data format: > > > > bclk = fs * 20 * 2 > > Sysclk = BCLKDIV * bclk = BCLKDIV * fs * 40 > > Sysclk = DACDIV * fs * 256 > > > > BCLKDIV/DACDIV = 256/40 = 32/5 > > > > But BCLKDIV/DACDIV can't be 32/5. So I want to support tdm slot. > > > > bclk = fs * slot_width * slots * channal. > > > > Do you think it make sense, or any other ideas? > > Reviving this question after two years :). > > After "ASoC: codec: wm8960: Relax bit clock computation" patch > > https://patchwork.kernel.org/patch/9636769/ > > we can now support S20_3LE for round rates like 8000, 16000, > 32000 and 48000. > > But not for 11025, 22050, 441000. Do you think it's worth exploring > "tdm slot" idea? I don't know exactly what it implies. > > Another idea, is to completely remove support for S20_3LE since it > is not trivial to derive bitclk from sysclk. > > What do you guys think? Does this problem still remain after the relaxed clock computation? The maths you quote depends on the derived BCLK being exactly the correct speed for the audio, that is no longer the case anymore. I would have thought the patch would cover both situations, as in if we can produce a suitable LRCLK, then we just pick a BCLK we can produce that is higher than we need. I don't see why that depends on things being a 48k based rate there. Am I missing something? Thanks, Charles