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From: Daniel Baluta <daniel.baluta@gmail.com>
Date: Mon, 3 Apr 2017 16:39:40 +0300
Message-ID: <CAEnQRZA_BzqY5ywkik0-+dCXj1C7ORzjh3Fnt_AM_e=HnaOKMg@mail.gmail.com>
Subject: Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver
 configure its bit clock and frame clock
To: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Cc: Zidan Wang <b50113@freescale.com>, Mark Brown <broonie@kernel.org>,
        Zidan Wang <zidan.wang@freescale.com>,
        Liam Girdwood <lgirdwood@gmail.com>, Jaroslav Kysela <perex@perex.cz>,
        tiwai@suse.de, Lars-Peter Clausen <lars@metafoo.de>,
        patches@opensource.wolfsonmicro.com, alsa-devel@alsa-project.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        shengjiu.wang@nxp.com, mihai.serban@nxp.com, viorel.suman@nxp.com
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On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
<ckeepax@opensource.wolfsonmicro.com> wrote:
> On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
>> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang <b50113@freescale.com> wrote:
>> > On Wed, Jan 14, 2015 at 07:27:03PM +0000, Mark Brown wrote:
>> >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
>> > I found it can't generate bclk for S20_3LE data format.
>> >
>> > For 2 channel S20_3LE data format:
>> >
>> > bclk = fs * 20 * 2
>> > Sysclk = BCLKDIV * bclk = BCLKDIV * fs * 40
>> > Sysclk = DACDIV * fs * 256
>> >
>> > BCLKDIV/DACDIV = 256/40 = 32/5
>> >
>> > But BCLKDIV/DACDIV can't be 32/5. So I want to support tdm slot.
>> >
>> > bclk = fs * slot_width * slots * channal.
>> >
>> > Do you think it make sense, or any other ideas?
>>
>> Reviving this question after two years :).
>>
>> After "ASoC: codec: wm8960: Relax bit clock computation" patch
>>
>> https://patchwork.kernel.org/patch/9636769/
>>
>> we can now support S20_3LE for round rates like 8000, 16000,
>> 32000 and 48000.
>>
>> But not for 11025, 22050, 441000. Do you think it's worth exploring
>> "tdm slot" idea? I don't know exactly what it implies.
>>
>> Another idea, is to completely remove support for S20_3LE since it
>> is not trivial to derive bitclk from sysclk.
>>
>> What do you guys think?
>
> Does this problem still remain after the relaxed clock
> computation? The maths you quote depends on the derived BCLK
> being exactly the correct speed for the audio, that is no longer
> the case anymore.
>
> I would have thought the patch would cover both situations, as in
> if we can produce a suitable LRCLK, then we just pick a BCLK we

That!

The problem for remaining rates is that we cannot derive the LRCLK

<snip>
+ for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
+ if (sysclk != dac_divs[j] * lrclk)
+ continue;
</snip>


> can produce that is higher than we need. I don't see why that
> depends on things being a 48k based rate there. Am I missing
> something?