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Date: Mon, 3 Apr 2017 14:54:36 +0100
From: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
To: Daniel Baluta <daniel.baluta@gmail.com>
CC: Zidan Wang <b50113@freescale.com>, Mark Brown <broonie@kernel.org>,
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Subject: Re: [alsa-devel][PATCH v2 2/2] ASoC: wm8960: Let wm8960 driver
 configure its bit clock and frame clock
Message-ID: <20170403135436.GV6986@localhost.localdomain>
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On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> <ckeepax@opensource.wolfsonmicro.com> wrote:
> > On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> > Does this problem still remain after the relaxed clock
> > computation? The maths you quote depends on the derived BCLK
> > being exactly the correct speed for the audio, that is no longer
> > the case anymore.
> >
> > I would have thought the patch would cover both situations, as in
> > if we can produce a suitable LRCLK, then we just pick a BCLK we
> 
> That!
> 
> The problem for remaining rates is that we cannot derive the LRCLK
> 
> <snip>
> + for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
> + if (sysclk != dac_divs[j] * lrclk)
> + continue;
> </snip>
> 

If you can't generate the LRCLK you either need a different
source clock or to use the PLL. You don't want to be trying to
pull 44.1k audio over a link that is clocked on a 48k based
clock.

Is the problem here that the PLL part of the code is making the
same assumption as the direct part of the code was, that the bclk
should be exact?

Thanks,
Charles